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DesignCon presents this five-part, live webinar series presented by expert engineers from the electronics chip, board, and systems industries. These free to attend LIVE 5-60 minute sessions walk attendees through use cases, propose various tools for solving a range of design problems, and expand viewers’ understanding of key engineering principles. All attendees will receive a discount code for the upcoming in-person DesignCon event.
Improved Methodology to Accurately Perform System Level Power Integrity Analysis Including an ASIC Die
Monday, November 7, 2022 at 1 p.m. Eastern Standard Time
Benjamin Dannan, Technical Fellow, Northrop Grumman
James Kuszewski, Consulting Engineer, Northrop Grumman
Modern ASIC-based systems can no longer be designed by rules of thumb when it comes to power integrity. The traditional methods of evaluating power integrity for an ASIC die on a substrate are generally lacking sufficient accuracy. The key element for system-level Power Distribution Network (PDN) analysis is a chip die model, which requires specialized EDA tools to create. These Electronic Design Automation (EDA) solutions typically create chip models using either vector-based or vectorless dynamic current profiles. Vector-based chip model solutions are challenging to create and typically do not cover the complete ASIC die use cases. In addition, the benefits of models created for the die, substrate, and PCB have multiple possible configurations such as lumped, distributed, looped and partial. This paper provides a novel workflow on the benefits of using lumped-looped models to improve efficiency, while achieving accuracy, and reducing the overall risk to a given system PDN. Lastly, this paper provides an improved methodology to determine if the voltage ripple at the die bumps on a substrate is violating the defined specification of the ASIC, and shows a method of evaluating the PDN target impedance across a system.
PCB Stackup & Launch Optimization in High-speed PCB Designs
Tuesday, November 8, 2022 at 1 p.m. Eastern Standard Time
Speaker: Shawn Tucker, Signal Integrity Engineer, Samtec
Validation of next generation systems requires high frequency instrument test access with system bandwidth needs exceeding 100 GHz. Compression mount vertical launch connectors are widely used for these applications due to the advantages of precision impedance, shielding, and standardization that coaxial designs offer, so this will be our focus. Balance trade-offs with material selection, stackup design, and RF launch optimization techniques being covered. With the help of engineering principles, mathematical equations, simulation, and measurements, we'll show theory and more importantly practical solutions for many of the issues encountered in high performance designs in a real-world system.
Exploring the Requirements for 224Gbps Channel Characterization Using Simulations & Measurements
Wednesday, November 9, 2022 at 1 p.m. Eastern Standard Time
Mike Resso, Signal Integrity Scientist, Keysight Technologies
Rick Rabinovich, Distinguished Engineer, Keysight Technologies
The pandemic has shifted many digital modernization projects within the internet infrastructure to occur more swiftly. Similar to the way cloud architectures have changed networking in the past decade, we now see rapid transitions to new technologies. In the next 2-3 years the future ethernet speed will evolve toward the 224 Gbps per lane. Consider, at this serial data rate, transition times are about 4 picoseconds and unit intervals are below 10 picoseconds for PAM-4 modulation. The development of reliable end-to-end copper communications channels require careful examination of semiconductor devices, packages, PCBs, connectors, and cable assemblies within this context.
Ensuring proper equalization schemes at both transmitter and receiver ends is a critical step of this strategic goal. This work highlights significant aspects and provides reasonable solutions for achieving feasible channel performances. This includes post-DFE eye opening at a given BER for an actual physical channel and compares to channel operating margin (COM). The objective is to present fine measurement techniques for accurately characterizing the channel, and for adequately developing equalization schemes at both TX and RX sides. This also includes the parametric adjustments to COM methodologies. These techniques are necessary for effectively exploring feasible design solutions.
How to Optimize TxFFE & What We Can Learn From the Optimization
Thursday, November 10, 2022 at 1 p.m. Eastern Standard Time
Speaker: Ransom Stephens, Consulting Senior Scientist at BitifEye Digital Solutions and Sage at Ransom’s Notes
Ever-increasing data rates demand more powerful transmitter feed-forward equalization (TxFFE): more taps and better simultaneous optimization of inter-symbol interference (ISI) correction and of noise. The complexity of tap optimization increases exponentially, each new tap introduces another dimension to the optimization equation. Multi-level modulation schemes like PAM4, PAM8, etc. add yet another level of complexity; since tap granularity is limited by the transmitter's digital to analog converter (DAC) resolution, the more symbols, the fewer available tap values per symbol. We begin by reviewing techniques for tuning taps in practice, called link training, and for calibration of TxFFE signals for compliance and diagnostic tests. We then address three important issues: First, the best test points for calibrating TxFFE taps – the transmitter output, the test fixture output, or the input to a compliance board. Second, the most effective patterns for analyzing the properties of TxFFE signals; we'll show the pros and cons of a simple step response versus test patterns that produce ISI to make the TxFFE effect explicit, and the impact of finite DAC resolution for both. And, finally, we consider what optimized TxFFE taps can tell us about the channel, a question pivotal for understanding link training.
Proper Ground Return Via Placement for 40+ Gbps Signaling
Friday, November 11, 2022 at 1 p.m. Eastern Standard Time
Michael Steinberger, Consultant Software Engineer, MathWorks
Donald Telian, SI Consultant, SiGuys
As signaling rates move beyond 40 Gbps a proper understanding of Ground Return Vias (GRVs) is imperative. For decades engineers have placed GRVs next to signal layer transitions based on best practices, with little understanding of relevant quantity and spacing. Place GRVs too far away or pinout a BGA's GRVs incorrectly and a signal via's insertion loss (IL) can drop 40dB. This paper explains the science behind GRVs using practical examples confirmed by measurement and simulation. GRV placement's relationship to data rate and impact on IL, RL, Via Impedance, and Crosstalk are described.