Predicting critical aspects of system performance requires accurate component models. This track addresses the creation & validation of silicon, substrates, and component-level models needed for system design and verification.

CFA topics of interest

• Serial channel I/O modeling
  • IBIS-AMI model generation, validation and simulation strategies
  • IBIS-AMI model quality and silicon correlation methodologies
  • Modeling emerging equalization technologies
  • Correlating COM vs. AMI models and results
• Memory (DDR, LPDDR, HBM, etc.) I/O modeling
  • DDRx IBIS-AMI model development and validation
  • Model support for DDRx controller DRAM DFE training
  • Power Aware Modeling for AMI
  • New techniques for modeling memory
• Power-aware modeling
  • Power-aware IBIS modeling for SSO simulation
  • Touchstone models for SI and Power
  • Silicon power modeling techniques
• On-chip power and mixed-signal modeling methodology
  • Analog/mixed signal and power design methods
  • Approaches for system-level modeling of I/O buffers and voltage regulators
  • Digital Power Controllers modeling, and correlation
  • Chip-level modeling of power simulations for PDN strategies
  • Mixed-signal behavioral models for SerDes phase-locked loops
  • Behavioral modeling of clock jitter and phase noise
  • Vertical Power Modeling

Integrating photonics or wireless technology into electrical designs presents unique design challenges at chip, board, and system level. This track deals with the issues associated with the design and integration of photonics and wireless ICs, 3D packaging involving optical and electrical interconnects for data communication, emerging wireless and mmWave applications such as 5G/6G, antenna in package integration, and automotive sensor applications such as Lidar or mmWave radar.

CFA topics of interest

• Technology:
  • Microwave photonics
  • Photonic ICs and interconnects
  • Co-Packaged Optics (CPO) & Near Package Optics (NPO)
  • Linear direct drive (no-retimer) optics
  • Optical transceivers, Lidar and sensors
  • Wireless interconnect technologies
  • Wireless and optical network convergence
  • mmWave radar for automotive and mobile applications
• Design, Layout & Assembly
  • Photonics and electrical components for 100/400/800/1600Gbps optical communications.
  • Lidar system integration and packaging
• Modeling & Simulation
  • Silicon Photonics passive components such as optical waveguides, transitions, mode converters, phase rotators.
  • Silicon Photonics phase shifters, attenuators, MZM, ring modulators, coherent transmitters and receivers
  • Electrical ICs such as laser driver, TIAs
  • Lasers and photo detectors
  • mmWave planar PCB circuits layout, modeling and simulation
  • 3D packaging of electro-optical ICs
  • Electro-optic AMI model simulation
• Compliance & Measurements
  • Measurement and testing of optical/electrical ICs, transceivers, sensors
  • Measurement and testing of RF/mmWave ICs and antenna in package modules

Printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the PCB’s modules and packages. This track considers those needs and analyzes the various solution options.

CFA topics of interest

• PCB, module, and package processing techniques
  • Fine registration improvements
  • Advanced stub mitigation including backdrilling
  • High aspect-ratio vias
  • MSAP-modified semi-additive processing
  • Novel manufacturing techniques
  • Copper profile advances – inner layer adhesion promotors
  • Build-up multilayers
• Advanced laminate and electrical characterization
  • Accurately predicting path losses
  • Impact of copper on characterization and design
  • Impact on materials for humidity, temperature, chemistries, special environments
  • Materials characterization and modeling
  • Thermal characterization and modeling
  • Advances in low loss laminates
  • Advances in copper surfaces including resin to copper adhesion techniques
  • Advances in thin dielectrics for signal layers
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
• PCB, module, and package design
  • Microvias, RF vias and thermal vias
  • Embedded optical channels
  • Embedded devices (active and passive)
  • Decoupling with Embedded Capacitor layers
  • Routing Techniques
  • Sockets and connectors
  • Hybrid board construction for performance and economy
• 3D printing and additive manufacturing
• Rigid-flex and multilayer flex circuit materials, design and manufacturing
• PCB and hybrid media advances for increased power delivery and thermal management
• How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths
• Other materials such as magnetic dielectrics and thermal management
• Automotive and sensor materials advances
• Sustainable PCB manufacturing

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, machine learning, virtual/augmented reality, and high-performance computing (HPC) present great challenges in interface design. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various designs in areas of Memory interface, 3DIC/SiP, and high-speed chip-to-chip interconnects.

CFA topics of interest

• Memory interface
  • Mobile memory designs (LPDDR, DDR-NAND, UFS)
  • Mainstream memory designs (DDR, GDDR, RLDRAM)
  • NV memory
  • Emerging memory interface (optical memory)
• 3DIC/SiP interface
  • HBM, HMC Chip-to-chip, and Wide I/O interfaces
  • Proprietary or emerging 3DIC/SiP designs
  • I/O interface design as applied to die/interposer/package technology
• High-speed parallel interface
  • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
  • Circuit architecture and techniques for improving signal bandwidth
  • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
  • Low-power designs
• Signal/power integrity simulation
  • Supply noise induced clock and data jitter analysis
  • Channel crosstalk, simultaneous switching noise, and statistical timing models
  • Circuit architecture and I/O design techniques to improve signal and power integrity

Design-oriented modeling simulation and analysis are required for cost-effective power and signal integrity (SI) performance optimization of chip, package, board, and chip+package+board+VRM combinations. This track covers the broad range of topics required to best address those needs for modern microprocessor and digital systems.

CFA topics of interest

• Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
• System issues affecting PCB/socket/package/chip/device power modeling
• Sub-system SIPI interaction and isolation: design and characterization
• Application specific end-to-end system modeling
• New technology design, including IoT design and 5G system co-design
• System-in-package (SiP), multi-chip package (MCP), chiplet or module design
• Co-package VRM system design, modeling & measurement
• Mixed-signal system design & interaction of protection devices
• First- and second-level interconnect analysis as it affects system performance
• System-level power and signal integrity
• System co-design for high-speed signaling
• System-level challenges of multi-voltage design
• Performance trade-offs: electrical, mechanical, thermal

System designers must resolve a complex set of tradeoffs among package/board/backplane/cable design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

CFA topics of interest

• Design, architecture and/or SI analysis of complete backplane and cable interconnect systems
• Backplane and cable signal conditioning
• Copper-fiber trade-offs and common port design challenges
• System interconnect and switch fabric architecture
• Flex PCB and other advanced PCB design tradeoffs and challenges
• Design verification (validation) and correlation
• PCI Express, Gen 5/6/7, Ethernet, and other standard-based architectures
• Next-gen high-speed serial link standards/MSA, e.g. 224Gb/s
• IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
• Effects of adaptative equalization on link margins
• End-to-end link design, ideas, and algorithms that optimize link performance and latency while meeting reach and power requirements
• SerDes design architectures and their influence on link development
• PAM-N vs NRZ vs other advanced modulation schemes system trade-offs/case studies
• Serial link system performance evaluation techniques (e.g. COM, Salz SNR)

Panel topics of interest

• 224Gb/s system design ideas and challenges (SerDes, package, PCB/Cable, modulation, coding)
• PCI-Express Gen 5, 6, and 7 design ideas and challenges
• Signal integrity design ideas and challenges for automotive applications

High-speed serial system impairments caused by jitter, noise, such as distortion, crosstalk, and ISI, can translate into bit, symbol, and frame errors. This track covers techniques for reducing errors in BER/SER/FER (bit/symbol/frame error ratio) through analysis of measurements, simulations, and models of components, subsystems, and systems.

CFA topics of interest:

• Measurement and modeling for Error ratio, SNDR (signal-to-noise & distortion ratio), TDECQ (Transmitter Dispersion Eye Closure Penalty Quaternary), ERL (effective return loss), R_LM (ratio of level-mismatch)/non-linearity and distortion analysis
• Measurements and modeling of burst errors; pre-FEC to post-FEC error propagation
• Modeling, simulation, and measurements of correlated and uncorrelated jitter, noise, crosstalk, reflection, and ISI (inter-symbol interference)
• Clock Recovery and Reference Clock impact. Analysis of clocks in time/frequency/phase domains. Embedded/forward clocking
• COM (channel operating margin) - applying COM to measurements
• PAM-n analysis for pre-FEC BER/SER and post-FEC FER minimization
• Standard compliance and requirements for measurement systems: bandwidth, noise floor, intrinsic jitter
• Stressed eye testing: Jitter and interference calibration, tolerance measurement, for FFE, DFE, MLSD
• Channel/test fixture de-embedding/embedding and modeling

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, synchronization, timing, detection, and FEC methods. This track covers design, modeling, analysis, implementation, and validation of such techniques.

CFA topics of interest

• Equalization techniques for high-speed serial links
• Adaptive equalization and tap optimization
• Back-channel training methods and performance
• CDR and PLL algorithms, modeling and realization
• Carrier synchronization for coherent systems
• FEC (forward error correction), error propagation, frame error rate (FER) analysis, modeling and implementation
• FEC encoder and decoder algorithms, hard/soft detection and decoding
• FEC techniques and analysis related to coding layers (e.g. Ethernet PCS/PMA)
• Advanced modulation and coding (e.g. PAM-n, QAM/coherent, Trellis Coded Modulation (TCM), concatenated code, etc.)
• Signal detection algorithms such as maximum likelihood sequence detection (MLSD)
• Signal processing and related modeling for optical links, non-retimed linear interfaces, components, circuits, and noise sources
• Power, latency and performance architectural trade-offs
• Lab validation of system performance and architecture choices
• SerDes device simulation (e.g. simulation of signal path and algorithms)
• Comparing simulation and measurement
• End-to-end channel analysis and compliance methodology
• Pseudo random and stress test data patterns and code frequency spectra
• Signal coding, scrambling and DC balance modeling

Panel and/or tutorial topics of interest

• Focus on joint optical and electrical link modeling and performance
• Tutorial on IEEE 802.3dj FEC

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and chips, including thermal and reliability considerations ̶̶̶̶  ­in HPC, AI and ML applications, for instance. It emphasizes the modeling and analysis of impedance, supply noise, and/or power induced jitter, and their impact on overall system performance.

CFA topics of interest

• System level PDN design strategy
  • Chip/package/board analysis and decoupling optimization
  • PDN performance versus cost, size, yield, reliability, etc.
  • System and PCB PDN modeling and simulation
  • PDN specifications, measurements, and correlation
  • System power noise and transients modeling and mitigation
  • Supply noise induced jitter analysis and optimization
  • Thermal / Power co-design
  • Vertical power integration and vertical power delivery
  • Very high current PDN design and validation
• Chip-level power distribution and regulation impact on system PDN performance
  • On-chip power grid inductance, resistance, and on-die decoupling
  • Dynamic and static voltage variations
  • On-chip regulator and power gating impact on power integrity
• Power supply design
  • DC/DC converter, VRD and VRM design including GaN, SIC and module technologies
  • Power supply design, dynamic response
  • Power efficiency management strategies
  • Power-aware architecture
  • Power modes management for portable & mobile electronics
  • Digital control loops
  • Low-voltage, high-power designs
  • VRM, VRD, and DC-DC converter modeling and simulation
  • AC-DC converters and its EMC and SI/PI impact on on-board, modules, and Data Centers
  • PMIC and its impact on PDN noise and power induced jitter
  • PDN optimization with PMIC

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

CFA topics of interest

• Design techniques to reduce or eliminate sources of EMI
• Near-field and far-field radiation computations and scan
• Pre- and post-qualification testing for emissions
• EMI radiation and suppression
• EMI system susceptibility
• Near-field coupling and crosstalk
• Emissions and interference modeling
• RFI/De-sense and co-existence for mobile electronic devices
• Noise characterization and containment
• EMI troubleshooting techniques
• Pre-qualification testing for immunity (radiated, ESD, etc.)
• Shielding at PCB, package, and system level
• EMI measurements and measurement techniques
• New shielding techniques and novel shielding materials
• Meeting compliance requirements
• Power supply consideration and noise effects for EMI/RFI
• EMI for high-density multi-port systems
• ESD modeling and measurements

Tutorial topic of interest

• Locating and fixing EMI problems in PCB areas

Advancements in measurement techniques are constantly being made for all aspects of signal and power integrity. This track focuses on the new techniques with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

CFA topics of interest

• Measurement Methods for SI, PI, and EMI/EMC
  • Classic measurements with modern instruments i.e., capturing a PRBS data pattern with picosecond UIs
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Power supply noise measurement methods for dynamic load response, ripple injection, etc.
  • Reference Planes, Partial S-Parameters, Behavioral Models, As-Fabricated, etc.
  • Measurement methods for Error ratio, SNDR (signal-to-noise & distortion ratio), ERL (effective return loss), R_LM (ratio of level-mismatch), Stressed Eye distortion, etc.
• ATE and multi-port test systems
  • ATE and sub-systems design validation and production at speed testing
  • ATE test sockets and multi-port switch matrix systems
  • Built in self-test methods with AI technology
• Hardware Technology and Architecture
  • Evolution of Network Analyzers, Oscilloscopes, Spectrum Analyzers
  • Next generation power delivery analyzers
  • One box does it all vs. traditional instruments vs. custom measurement systems
  • Machine learning for measurement systems
• Application Specific Measurements for Emerging Technologies
  • Measurement methods for compliance with PAM4, Ethernet, PCIe, USB, DDR, etc.
  • Inter-Pair skew for low latency in 5G, 6G, AI processing, etc
  • Extreme environments such as automotive, quantum, etc
  • PI challenges with GaN for low-power IoT, medical, consumer products, etc.
• Fixture Design and De-embedding
  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc
  • IEEE and IPC standards for fixture mitigation and material properties measurements
  • Fixture de-embedding techniques including EM-solver and measure-based models
  • Mixed standard calibration methods for non-coaxial reference planes
  • Comparing calibration methodologies: uncertainty and residual error of calibration methods
  • S-Parameter quality, causality, and passivity of measured data

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track includes passive link analysis and optimization for industry standards (10G, 28G 100G, 400G, PCIE, USB, SATA, DDR) with the use of electromagnetic and microwave signal integrity analysis techniques as well as validation with measurements.

CFA topics of interest

• Signal integrity analysis with RF/Microwave techniques
• Electromagnetic analysis of interconnects
• Interconnect analysis validation with measurements
• S-parameters in analysis of broadband interconnect systems
• Techniques for interconnect de-embedding
• Passive equalization and filtering
• Analysis of losses, dispersion, coupling, cross talk, and mode conversion in interconnects
• Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
• Electromagnetic modeling of channels including PCB traces, vias, packages, cables, fiber weave effects, and connectors
• Simulation modeling and analysis of interaction between power distribution networks and signal interconnects
• Via and via array design and optimization including BGAs, pin fields
• Gigahertz and Terahertz interconnects
• Analysis dealing with Industry standards Impedance specifications vs channel modeling issues
• Packages, chiplets and interposer interconnect design and optimization
• Stackup optimization for impedance losses via-hole design

Machine-learning algorithms can efficiently derive models for electronics and system design automation and enable fast, accurate design and verification of microelectronic circuits and systems. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. Machine learned generative models cover the entire solution space vs tradition discriminative models. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

CFA topics of interest

• Static and dynamic neural network models for high-speed channels and SerDes
• Channel and SerDes performance optimization using PCA generative models
• ML and DoE techniques for optimizing designs with numerous parameter options
• Generative and Bayesian surrogate models for response surface approximation
• Early predictive models for design planning
• Machine learning for proactive hardware failure predictions
• Supervised and un-supervised deep learning for hardware system performance tuning
• ML techniques for improved rational function model extraction from S-parameters
• GPU/TPU accelerated SerDes and channel simulation
• Automated high-speed PCB layout design using deep learning
• ML model portability & reusability across tools and tool flows
• Training and inference tradeoffs for speed and accuracy
• AI/ML assisted design for SI/PI for single-multi die, interposer & packaging
• AI/ML assisted design for EMC
• AI/ML assisted design for thermal analysis
• ML and AI techniques for fast measurement adaptation/optimization, device characterization, and DFX (design for everything)
• Digital twins for real time dynamic performance optimization