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The Nation’s Leading Electronic Design Conference


  • 14 track conference program created 
    by engineers
  • Boot camps, tutorials, panel discussions and  technical sessions
  • Additional Drive World track on automotive electronics and intelligence

Design Insights to Power Your Future

As the electronic industry surges ahead, so does the need for practical insights and solutions to engineer the next generation of products. Enter DesignCon. With technical paper sessions, panels, tutorials, and boot camps spanning 14 tracks, DesignCon’s three-day conference program provides the information you need to solve design challenges now and plan how to improve designs in the future.

Covering All Aspects of Electronic Design

Hosted in Silicon Valley, the heart of electronics innovation, DesignCon addresses chip, board, and system challenges facing design engineers. Sessions are provided for all levels of learning, with information for experienced engineers, recent graduates, and everyone in between.

From foundational to applicational, DesignCon conference areas include:

  • Signal and power integrity
  • Chip I/O and power modeling
  • Photonics and wireless in electrical design
  • Materials and processing for PCBs, modules, and packages
  • Advanced I/O interface design
  • High-speed link design
  • Signal processing, equalization, and coding/FEC
  • Power integrity in power distribution networks
  • Electromagnetic compatibility and interference
  • Test and measurement methodology
  • Interconnects modeling and analysis
  • Machine learning and AI
  • 5G and communications

Explore by area of interest with education themes in automotive, autonomous, consumer electronics, Internet of Things (IoT), and medical that will be addressed in multiple conference and theater sessions and represented at exhibits on the expo floor.

Curated “By Engineers For Engineers”

Created by our Technical Program Committee (TPC)—an expert panel of approximately 100 industry professionals — the DesignCon curriculum is reviewed and updated each year to meet the needs of our ever-evolving industry. DesignCon sets the industry standard for education and technology conferences, offering today's mission-critical information for people designing tomorrow's electronics products.

Drive World Conference

DesignCon once again welcomes Drive World, offering additional conference content to DesignCon All-Access and 2-Day conference attendees in the areas of automotive electronics and intelligence. Session topics include:

  • Security & Safety
  • Sensing Technologies
  • Autonomous & ADAS
  • Connectivity & Infotainment

Drive World expands to support electric vehicle technology education in addition to sessions in the areas of automotive electronics and intelligence. 

2025 Conference Tracks

Below is a description of each DesignCon 2025 track, including sample topic and session suggestions for Call for Abstracts submissions.

Click on a track name for more details.

Die, chiplet, optic, interposer, breakout, and packaging decisions can make or break a high-performance interface. This track covers a wide variety of signal and power integrity topics at the die, chiplet, interposer, packaging, and system interface levels. This includes SoC issues, multi-chip integration, chiplet ecosystems, CPC/NCP chip and near packaged copper-optical transitions, power delivery networks, related noise and jitter mitigation strategies.

CFA topics of interest

  • Chip/near packaged optics and transition from die to transceiver
  • Chip/near packaged copper transition from die to system board
  • Signal Integrity (SI), Power Integrity (PI), and Power Distribution Network (PDN) considerations in chip and packaging designs
  • Implications of interactions between chip-level and systems design decisions
  • On-chip and chip-to-chip, chiplet, Multi-Chip-Module (MCM) interconnect, and chip to module (connector) interconnect design and analysis
  • 2.5D/3D interconnect and interposer design as applied to die/interposer/package technology
  • Overcoming the SI/PI impact of higher reliability design constraints for automotive and space applications
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-sequencing design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration/learning techniques to improve signal and power integrity
  • Clock and reset strategies to improve signal and power integrity
  • Through-silicon vias (TSV)
  • System-in-Package (SiP) partition and IP integration
  • Design validation, correlation, and verification
  • AI Assisted Design Methodologies

Predicting critical aspects of system performance requires accurate sub-systems and component models. This track addresses the creation and validation of silicon, substrates, and component-level models needed for system design and verification.

CFA topics of interest

  • Serial channel I/O modeling
    • IBIS-AMI model generation, validation, and simulation strategies
    • IBIS-AMI model quality and silicon correlation methodologies
    • Modeling emerging equalization technologies
    • Correlating COM vs. AMI models and results
  • Power delivery modeling
    • Cost benefit analysis of power delivery architecture for high power chips
    • On package topology modeling for next gen power delivery devices 
    • Modeling fault management and repairability predictions
    • Power quality and reliability modeling
    • Lateral, semi lateral, and vertical power modeling
  • Memory (DDR, LPDDR, HBM, etc.) I/O modeling
    • DDRx IBIS-AMI model development and validation
    • Model support for DDRx controller DRAM DFE training
    • Power-aware modeling for AMI
    • New techniques for modeling memory
  • Power-aware modeling
    • Power-aware IBIS modeling for SSO simulation
    • Touchstone models for SI and Power
    • Silicon power modeling techniques
  • On-chip power and mixed-signal modeling methodology
    • Analog/mixed signal and power design methods
    • Approaches for system-level modeling of I/O buffers and voltage regulators
    • Digital Power Controllers modeling, and correlation
    • Chip-level modeling of power simulations for PDN strategies
    • Mixed-signal behavioral models for SerDes phase-locked loops
    • Behavioral modeling of clock jitter and phase noise
    • Vertical power modeling

Integrating photonics or wireless technology into electrical designs presents unique design challenges at chip, board, and system level. This track deals with the issues associated with the design and integration of photonics and wireless ICs, 3D packaging involving optical and electrical interconnects for data communication, co-packaged direct drive and retimed optics, and emerging wireless and mmWave applications.

CFA topics of interest

  • Technology
    • Microwave photonics
    • Photonic ICs and interconnects
    • Co-Packaged Optics (CPO) & Near Package Optics (NPO)
    • Linear direct drive (no-retimer) optics
    • Optical transceivers, Lidar and sensors
    • Wireless interconnect technologies
    • 5G/6G, mmWave radar, antenna in package
    • Wireless and optical network convergence
    • mmWave radar for automotive and mobile applications
    • Electro-optical transceiver chiplets
  • Design, Layout & Assembly
    • Photonics and electrical components for 100/400/800/1600Gbps optical communications
    • Lidar system integration and packaging
  • Modeling & Simulation
    • Silicon photonics passive components such as optical waveguides, transitions, mode converters, phase rotators
    • Silicon photonics phase shifters, attenuators, MZM, ring modulators, coherent transmitters and receivers
    • Electrical ICs such as laser driver, TIAs
    • Lasers and photo detectors
    • mmWave planar PCB circuits layout, modeling, and simulation
    • 3D packaging of electro-optical ICs
    • Electro-optic AMI model simulation
  • Compliance & Measurements
    • Measurement and testing of optical/electrical ICs, transceivers, sensors
    • Photonics wafer probing and fiber alignment
    • Measurement and testing of RF/mmWave ICs and antenna in package modules

Printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the PCB’s modules and packages. This track considers those needs and analyzes the various solution options.

CFA topics of interest

  • PCB, module, and package processing techniques
    • Fine registration improvements
    • Advanced stub mitigation including backdrilling
    • High aspect-ratio vias
    • MSAP-modified semi-additive processing
    • Novel manufacturing techniques
    • Copper profile advances – inner layer adhesion promotors
    • Build-up multilayers
  • Advanced laminate and electrical characterization
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Impact on materials for humidity, temperature, chemistries, special environments
    • Materials characterization and modeling
    • Thermal characterization and modeling
    • Advances in low loss laminates
    • Advances in copper surfaces including resin to copper adhesion techniques
    • Advances in thin dielectrics for signal layers
    • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • PCB, module, and package design
    • Microvias, RF vias and thermal vias
    • Embedded optical channels
    • Embedded devices (active and passive)
    • Decoupling with embedded capacitor layers
    • Routing techniques
    • Sockets and connectors
    • Hybrid board construction for performance and economy
  • 3D printing and additive manufacturing
  • Rigid-flex and multilayer flex circuit materials, design and manufacturing
  • PCB and hybrid media advances for increased power delivery and thermal management
  • How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths
  • Other materials such as magnetic dielectrics and thermal management
  • Automotive and sensor materials advances
  • Sustainable PCB manufacturing

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, machine learning, virtual/augmented reality, and high-performance computing (HPC) present great challenges in interface design. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various designs in areas of memory interface, such as UCIe, 3DIC/SiP, and high-speed chip-to-chip interconnects.

CFA topics of interest

  • Memory interface
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
    • NV memory
    • Emerging memory interface (optical memory)
  • HBM, Wide I/O Interfaces
    • HBM, HMC chip-to-chip, and wide I/O interfaces
    • 2.5D/3D interconnect and interposer design
  • Chiplet/Multi-die/3DIC/SiP
    • I/O design optimizations for on-chip, chiplets and chip to chip links
    • Proprietary or emerging 3DIC/SiP designs
    • I/O interface design as applied to die/interposer/package technology
  • High-speed parallel interface
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
    • Circuit architecture and techniques for improving signal bandwidth
    • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
    • Methologies for design space exploration
    • Low-power designs
  • Signal/power integrity modeling and simulation
    • Supply noise induced clock and data jitter analysis
    • Channel crosstalk, simultaneous switching noise, and statistical timing models
    • Circuit architecture and I/O design techniques to improve signal and power integrity

Design-oriented modeling simulation and analysis are required for cost-effective power and signal integrity (SI) performance optimization of chip, package, board, and chip+package+board+VRM combinations. This track covers the broad range of topics required to best address those needs for modern CPU/GPU and digital systems.

CFA topics of interest

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • System issues affecting PCB/socket/package/chip/device power modeling
  • Sub-system SIPI interaction and isolation: design and characterization
  • Application specific end-to-end system modeling
  • New technology design, including IoT design and 5G system co-design
  • System-in-package (SiP), multi-chip package (MCP), chiplet or module design, 2.5D/3DIC
  • Co-package VRM system design, modeling and measurement
  • Mixed-signal system design and interaction of protection devices
  • First- and second-level interconnect analysis as it affects system performance
  • System-level power and signal integrity
  • System co-design for high-speed signaling
  • System-level challenges of multi-voltage design
  • Performance trade-offs: electrical, mechanical, thermal management (air, liquid cooling)

System designers must resolve a complex set of tradeoffs among package/board/backplane/cable design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

CFA topics of interest

  • Design, architecture and/or SI analysis of complete backplane and cable interconnect systems
  • Backplane and cable signal conditioning
  • Copper-fiber trade-offs and common port design challenges
  • System interconnect and switch fabric architecture
  • Flex PCB and other advanced PCB design tradeoffs and challenges
  • Design verification (validation) and correlation
  • PCI Express, Gen 5/6/7, Ethernet, and other standard-based architectures
  • Next-gen high-speed serial link standards/MSA, e.g. 224Gb/s
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Effects of adaptative equalization on link margins
  • End-to-end link design, ideas, and algorithms that optimize link performance and latency while meeting reach and power requirements
  • SerDes design architectures and their influence on link development
  • PAM-N vs. NRZ vs. other advanced modulation schemes system trade-offs/case studies
  • Serial link system performance evaluation techniques (e.g. COM, Salz SNR)
  • AI/ML techniques for high-speed link design optimization
Panel topics of interest
  • 224Gb/s system design ideas and challenges (SerDes, package, PCB/Cable, modulation, coding)
  • PCI-Express Gen 5, 6, and 7 design ideas and challenges
  • Signal integrity design ideas and challenges for automotive/HPC/AI/ML applications
  • Challenges and ideas in adaptative equalization across vendors in real-world environment

High-speed serial system impairments caused by jitter, noise, distortion, crosstalk, and ISI, can translate into bit, symbol, and frame errors. This track covers techniques for reducing errors, BER/SER/FLR (bit/symbol/frame loss ratio) through analysis of measurements, simulations, and models of components, subsystems, and systems.

CFA topics of interest:

  • Measurement and modeling for error ratio, SNDR (signal-to-noise & distortion ratio), ERL (effective return loss), RLM (ratio of level-mismatch)/non-linearity and distortion analysis
  • Expansion of penalty-based measurements, such as TDECQ (Transmitter Dispersion Eye Closure Penalty Quaternary) in optical to EECQ (Electrical Eye Closure Quaternary) in electrical
  • Measurements and modeling of burst errors; pre-FEC to post-FEC error propagation
  • Modeling, simulation, and measurements of correlated and uncorrelated jitter, noise, crosstalk, reflection, and ISI (inter-symbol interference)
  • Correlation of performance between advanced model MLSD based simulation and physical measurements of the systems
  • Clock recovery and reference clock impact. Analysis of clocks in time/frequency/phase domains. Embedded/Common/Forward clocking methodologies
  • COM (channel operating margin) - applying COM to measurements
  • PAM-n and QAM-n analysis and measurements for pre-FEC BER/SER and post-FEC FLR minimization
  • Standard compliance and requirements for measurement systems: bandwidth, noise floor, intrinsic jitter
  • Stressed eye testing: Jitter and interference calibration, tolerance measurement, for FFE, DFE, MLSD
  • Channel/test fixture de-embedding/embedding and modeling

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, synchronization, timing, detection, and FEC methods. This track covers design, modeling, analysis, implementation, and validation of such techniques.

CFA topics of interest

  • Power, latency and performance architectural trade-offs for emerging applications (AI/ML, 6G, HPC, etc.)
  • Equalization, detection, FEC techniques for energy efficient interfaces (EEI): retimed optics (CDR/DSP), non-retimed linear optics (LPO), and co-packaged optics (CPO)
  • COM methodologies and optimization of reference architecture, equalization, and detection
  • End-to-end channel analysis and compliance methodology
  • Signal detection algorithms such as maximum likelihood sequence detection (MLSD)
  • Advanced modulation and coding (e.g. PAM-n, QAM/coherent, Trellis Coded Modulation (TCM), concatenated code, etc.)
  • FEC (forward error correction), error bursts/propagation, frame error rate (FER) analysis, modeling and implementation
  • FEC encoder and decoder algorithms, hard/soft detection and decoding
  • FEC techniques and analysis related to coding layers (e.g. Ethernet PCS/PMA)
  • Signal processing and related modeling for optical links, components, circuits, and noise sources
  • Equalization techniques for high-speed serial links
  • Adaptive equalization and tap optimization
  • Back-channel training methods and performance
  • CDR and PLL algorithms, modeling, and realization
  • Carrier synchronization for coherent and light-weight coherent systems
  • Lab validation of system performance and architecture choices
  • SerDes device simulation (e.g. simulation of signal path and algorithms)
  • Comparing simulation and measurement
  • Pseudo random and stress test data patterns and code frequency spectra
  • Signal coding, scrambling and DC balance modeling

Panel and/or tutorial topics of interest

  • Focus on joint optical and electrical link modeling and performance
  • AI use cases for high-speed signal processing, equalization, and FEC

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and chips, including thermal and reliability considerations ̶̶̶̶ ­in HPC, AI, and ML applications, for instance. It emphasizes the modeling and analysis of impedance, supply noise, and/or power induced jitter, and their impact on overall system performance.

CFA topics of interest

  • System level PDN design strategy
    • HPC, EV, AI, and ML applications
    • Chip/package/board analysis and decoupling optimization
    • PDN performance vs. cost, size, yield, reliability, etc.
    • System and PCB PDN modeling and simulation
    • PDN specifications, measurements, and correlation
    • System power noise and transients measurement, modeling and mitigation
    • Electro-thermal analysis and reliability
    • Power-induced crosstalk
    • Vertical power integration and vertical power delivery
    • Very high current PDN design and validation
  • Chip-level power distribution and regulation impact on system PDN performance
    • On-chip power grid inductance, resistance, and on-die decoupling
    • Dynamic and static voltage variations
    • On-chip regulator and power gating impact on power integrity
  • Power supply design
    • DC-DC converter, VRD and VRM design including GaN, SIC, and module technologies
    • Dynamic response and digital control loops
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management for portable & mobile electronics
    • Low-voltage, high-power designs
    • VRM, VRD, and DC-DC converter modeling and simulation
    • EMC and SI/PI impact of AC-DC converters on-board, modules, and Data Centers
    • PMIC and its impact on PDN noise and power induced jitter
    • PDN optimization with PMIC

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMC/EMI issues. This track raises the awareness and the impact for design and systems engineers involved in circuit architecture, supply designs, and interface performance. It looks at power distribution network design, modeling and analysis on boards, packages, and chips in order to mitigate possible issues and improve products in the early design stage.

CFA topics of interest

  • Design techniques to reduce or eliminate sources of EMI
  • Near-field and far-field radiation computations and scan
  • Pre- and post-qualification testing for emissions
  • EMI radiation and suppression
  • EMI system susceptibility
  • Electromagnetic analysis of radiating structures
  • Near-field coupling and crosstalk
  • Emissions and interference modeling
  • RFI/de-sense and co-existence for mobile electronic devices
  • Noise characterization and containment
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Shielding at PCB, package, and system level
  • EMI measurements and measurement techniques
  • New shielding techniques and novel shielding materials
  • Meeting compliance requirements
  • AI and Machine Learning for EMC measurement systems
  • Power supply consideration and noise effects for EMI/RFI
  • Signal and Power Optimization for reducing emissions
  • EMI for high-density multi-port systems
  • ESD modeling and measurements

Tutorial topic of interest

  • Locating and fixing EMI problems in PCB areas
  • EMC design ideas and challenges for automotive applications

Advancements in measurement techniques are constantly being made for all aspects of signal and power integrity. This track focuses on the new techniques with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

CFA topics of interest

  • Measurement Methods for SI, PI, and EMI/EMC
    • Classic measurements with modern instruments i.e., capturing a PRBS data pattern with picosecond UIs
    • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
    • Power supply noise measurement methods for dynamic load response, ripple injection, very low impedences, etc.
    • Reference planes, partial S-parameters, behavioral models, as-fabricated, etc.
    • Measurement methods for error ratio, SNDR (signal-to-noise & distortion ratio), ERL (effective return loss), RLM (ratio of level-mismatch), stressed eye distortion, power spectral density, etc.
    • Measurement and validation of chiplets and substrates
  • ATE and Multi-port Test Systems
    • ATE and sub-systems design validation and production at speed testing
    • ATE test sockets and multi-port switch matrix systems
    • Built in self-test methods with AI technology
  • Hardware Technology and Architecture
    • Evolution of network analyzers, oscilloscopes, and spectrum analyzers
    • Next generation power delivery analyzers
    • One box does it all vs. traditional instruments vs. custom measurement systems
    • Machine learning for measurement systems
  • Application Specific Measurements for Emerging Technologies
    • Measurement methods for compliance with standards
    • Inter-pair skew for low latency in 5G, 6G, AI processing, etc.
    • Extreme environments such as automotive and quantum
    • PI challenges with GaN for low-power IoT, medical, consumer products, etc.
  • Fixture Design and De-embedding
    • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
    • IEEE and IPC standards for fixture mitigation and material properties measurements
    • Fixture de-embedding techniques including EM-solver and measure-based models
    • Mixed standard calibration methods for non-coaxial reference planes
    • Comparing calibration methodologies: uncertainty and residual error of calibration methods
    • S-parameter quality, causality, and passivity of measured data
    • Relationships between time domain and frequency domain measurements

Panel topic of interest:

  • Measurement and validation

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track includes passive link analysis and optimization for industry standards (10G, 28G, 100G, 400G, PCIE, USB, SATA, DDR, UCIe) with the use of electromagnetic and microwave signal integrity analysis techniques as well as validation with measurements.

CFA topics of interest

  • Signal integrity analysis with RF/microwave techniques
  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • Techniques for interconnect de-embedding
  • Passive equalization and filtering
  • Analysis of losses, dispersion, coupling, cross talk, and mode conversion in interconnects
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines
  • Electromagnetic modeling of channels including PCB traces, vias, packages, cables, fiber weave effects, and connectors
  • Simulation modeling and analysis of interaction between power distribution networks and signal interconnects
  • Via and via array design and optimization including BGAs and pin fields
  • Gigahertz and Terahertz interconnects
  • Analysis dealing with competing impedance specifications vs. channel modeling issues
  • Packages, chiplets, and interposer interconnect design and optimization

Machine-learning algorithms can efficiently derive models for electronics and system design automation and enable fast, accurate design and verification of microelectronic circuits and systems. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. Machine learned generative models cover the entire solution space vs. tradition-discriminative models. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

CFA topics of interest

  • Static and dynamic neural network models for high-speed channels and SerDes
  • Channel and SerDes performance optimization using PCA generative models
  • ML and DoE techniques for optimizing designs with numerous parameter options
  • Generative and Bayesian surrogate models for response surface approximation
  • Early predictive models for design planning
  • Machine learning for proactive hardware failure predictions
  • Supervised and un-supervised deep learning for hardware system performance tuning
  • ML techniques for improved rational function model extraction from S-parameters
  • GPU/TPU accelerated SerDes and channel simulation
  • Automated high-speed PCB layout design using deep learning
  • ML model portability & reusability across tools and tool flows
  • Training and inference tradeoffs for speed and accuracy
  • AI/ML assisted design for SI/PI for single-multi die, interposer & packaging
  • AI/ML assisted design for EMC
  • AI/ML assisted design for thermal analysis
  • ML and AI techniques for fast measurement adaptation/optimization, device characterization, and DFX (design for everything)
  • Digital twins for real time dynamic performance optimization
  • Large language models and Gen AI for SI/PI

Session Formats

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Boot Camps

Get up to speed — fast — with all-day boot camps covering core industry concepts, including signal integrity, power integrity, and more.

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DesignCon’s three-hour tutorial sessions offer rich learning opportunities by allowing the speakers to cover timely topics in depth.

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Panel Discussions

These 75-minute panel discussions will host three or more visionaries as they present their insights and discuss opinions on a carefully curated topic. 

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Technical Sessions

Presented in 45-minute sessions, the technical papers and their presentations provide new research, case studies and applications from thought leaders in the community.