Die, chiplet, optic, interposer, breakout, and packaging decisions can make or break a high-performance interface. This track covers a wide variety of signal and power integrity topics at the die, chiplet, interposer, packaging, and system interface levels. This includes fabrication technology, SoC issues, multi-chip integration, chiplet ecosystems, co-packaged optics, power delivery networks, related noise and jitter mitigation strategies.

CFA topics of interest

• Chip/near packaged optics and transition from die to transceiver
• Chip/near packaged copper transition from die to system board
• Signal Integrity (SI), Power Integrity (PI), and Power Distribution Network (PDN) considerations in chip and packaging designs
• Implications of interactions between chip-level and systems design decisions
• On-chip and chip-to-chip, chiplet, Multi-Chip-Module (MCM) interconnect, and chip to module (connector) interconnect design and analysis
• 2.5D/3D interconnect and interposer design as applied to die/interposer/package technology
• Overcoming the SI/PI impact of higher reliability design constraints for automotive and space applications
• Simultaneous switching noise (SSN) and crosstalk suppression techniques
• On-chip instrumentation and measurement
• On-chip current modeling and correlation
• On-chip noise-to-jitter modeling and circuit implications/strategies
• Multi-voltage and power-sequencing design for SOCs and circuit-level implications
• Low-power strategies and implementation
• Circuit and interface calibration/learning techniques to improve signal and power integrity
• Clock and reset strategies to improve signal and power integrity
• Through-silicon vias (TSV) and other Advanced Interconnects like UCIe
• System-in-Package (SiP) partition and IP integration
• Design validation, correlation, and verification
• AI assisted design methodologies

Accurate sub-system and component models are crucial for predicting critical aspects of system performance. This track focuses on the creation and validation of essential silicon, substrate, and component-level models that are necessary for system design and verification.

CFA topics of interest

• Serial channel I/O modeling
  • Generation, validation, and simulation strategies for IBIS-AMI models
  • Methodologies for assessing IBIS-AMI model quality and silicon correlation
  • Modeling of emerging equalization technologies
  • Correlation between COM and AMI models and their results
  • Improved SPICE to IBIS model generation flows for accuracy
• Power delivery modeling
  • Cost benefit analysis of power delivery architecture for high power chips
  • On-package topology modeling for next-generation power delivery devices
  • Predictions for fault management and repairability
  • Power quality and reliability modeling
  • Lateral, semi-lateral, and vertical power modeling approaches
• Memory I/O Modeling (DDR, LPDDR, HBM, etc.) 
  • Development and validation of DDRx IBIS-AMI models
  • Model support for DDRx controller DRAM DFE training
  • Power-aware modeling techniques for AMI
  • Innovative modeling approaches for memory technologies
• Power-Aware Modeling
  • Power-aware IBIS modeling for simultaneous switching output (SSO) simulations
  • Touchstone models for signal integrity and power analysis
  • Techniques for silicon power modeling
• On-Chip Power and Mixed-Signal Modeling Methodologies
  • Analog/mixed-signal and power design methodologies
  • System-level modeling approaches for I/O buffers and voltage regulators
  • Digital power controller modeling and correlation techniques
  • Chip-level modeling strategies for power distribution network (PDN)
  • Development of mixed-signal behavioral models for SerDes phase-locked loops
  • Behavioral modeling of clock jitter and phase noise
  • Vertical power modeling  techniques
• Effectiveness and accuracy of PCB power delivery modeling
  • Multi-lam stackup and HDI PCB
  • Thermal-electrical modeling of PCBs
  • Vertical power on PCBs
  • Embedded components

Integrating photonics and wireless technology into electrical designs presents distinct challenges at the chip, board, and system levels. This track focuses on design and integration challenges of photonics and wireless ICs, including 3D packaging that combines optical and electrical interconnects, co-packaged direct drive and retimed optics, for emerging applications in artificial intelligence, machine learning, wireline data  ommunication, wireless and mmWave technologies.

CFA topics of interest

• Technology
  • Microwave photonics
  • Photonic ICs and interconnects
  • Co-Packaged Optics (CPO) & Near Package Optics (NPO)
  • Linear direct drive (no-retimer), Linear Receive Optics (LRO)
  • Optical PCIe and OCI
  • Optical transceivers, Lidar and sensors
  • Wireless interconnect technologies
  • 5G/6G, mmWave radar, antenna in package
  • Wireless and optical network convergence
  • mmWave radar for automotive and mobile applications
  • mmWave technology and dielectric waveguides for wireline applications
  • Electro-optical transceiver chiplets
  • New materials and technology for higher speed optical modulation and detection
• Design, Layout & Assembly
  • Photonics and electrical components for 100/400/800/1600/3200 Gbps optical communications
  • Lidar system integration and packaging
• Modeling & Simulation
  • Silicon photonics passive components such as optical waveguides, transitions, mode converters, phase rotators
  • Silicon photonics phase shifters, attenuators, MZM, ring modulators, EMLs, coherent transmitters and receivers
  • Electrical ICs such as laser driver, TIAs, integrated passive devices for silicon photonics
  • Lasers and photo detectors
  • mmWave planar PCB circuits layout, modeling, and simulation
  • 3D packaging of electro-optical ICs
  • Electro-optic link simulation including AMI model creation
• Compliance & Measurements
  • Measurement and testing of optical/electrical ICs, transceivers, sensors
  • Photonics wafer probing and fiber alignment
  • Measurement and testing of RF/mmWave ICs and antenna in package modules

Printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the PCB’s modules and packages. This track considers those needs and analyzes the various solution options.

CFA topics of interest

• PCB, module, and package processing techniques
  • Fine registration improvements
  • Advanced stub mitigation including backdrilling
  • High aspect-ratio vias
  • MSAP-modified semi-additive processing
  • Novel manufacturing techniques
  • Copper profile advances – inner layer adhesion promotors
  • Build-up multilayers
• Advanced laminate and electrical characterization
  • Accurately predicting path losses
  • Impact of copper on characterization and design
  • Impact on materials for humidity, temperature, chemistries, special environments
  • Materials characterization and modeling
  • Thermal characterization and modeling
  • Advances in low loss laminates
  • Advances in copper surfaces including resin to copper adhesion techniques
  • Advances in thin dielectrics for signal layers
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
• PCB, module, and package design
  • Microvias, RF vias and thermal vias
  • Embedded optical channels
  • Embedded devices (active and passive)
  • Decoupling with embedded capacitor layers
  • Routing techniques
  • Sockets and connectors
  • Hybrid board construction for performance and economy
• 3D printing and additive manufacturing
• Rigid-flex and multilayer flex circuit materials, design and manufacturing
• PCB and hybrid media advances for increased power delivery and thermal management
• How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths
• Other materials such as magnetic dielectrics and thermal management
• Automotive and sensor materials advances
• Sustainable PCB manufacturing

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, machine learning, virtual/augmented reality, and high-performance computing (HPC) present great challenges in interface design. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various designs in areas of memory interface, such as UCIe, 3DIC/SiP, and high-speed chip-to-chip interconnects. Use of AI/ML techniques to manage the complexity of advanced interface design and optimize trade-offs among power, cost, and latency.

CFA topics of interest

• Memory interface
  • Mobile memory designs (LPDDR, DDR-NAND, UFS)
  • Mainstream memory designs (DDR, GDDR, RLDRAM)
  • NV memory
  • Emerging memory interface (optical memory)
• HBM, Wide I/O Interfaces
  • HBM, HMC chip-to-chip, and wide I/O interfaces
  • 2.5D/3D interconnect and interposer design
• Chiplet/Multi-die/3DIC/SiP
  • I/O design optimizations for on-chip, chiplets and chip to chip links
  • Proprietary or emerging 3DIC/SiP designs
  • I/O interface design as applied to die/interposer/package technology
• High-speed parallel interface
  • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
  • Circuit architecture and techniques for improving signal bandwidth
  • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
  • Methologies for design space exploration
  • Low-power designs
• Signal/power integrity modeling and simulation
  • Supply noise induced clock and data jitter analysis
  • Channel crosstalk, simultaneous switching noise, and statistical timing models
  • Circuit architecture and I/O design techniques to improve signal and power integrity
• Applied AI/ML for Memory/HBM, chiplet, multi-die & 3DIC/SiP integrations
  • AI/ML techniques to manage and optimize the complexity of advanced interface design
  • Use cases can include machine learning methods and algorithms to speed up or assist interface designs including IO and interconnect

Design-oriented modeling simulation and analysis are required for cost-effective power and signal integrity (SI) performance optimization of chip, package, board, and chip+package+board+VRM combinations. This track covers the broad range of topics required to best address those needs for modern CPU/GPU and digital systems.

CFA topics of interest

• Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
• System issues affecting PCB/socket/package/chip/device power modeling
• Sub-system SI/PI interaction and isolation: design and characterization
• Application specific end-to-end system modeling
• New technology design, including IoT design and 5G system co-design
• System-in-package (SiP), multi-chip package (MCP), chiplet or module design, 2.5D/3DIC, UCIe
• Co-package VRM system design, modeling and measurement
• Mixed-signal system design and interaction of protection devices
• First- and second-level interconnect analysis as it affects system performance
• System-level power and signal integrity
• System co-design for high-speed signaling
• System-level challenges of multi-voltage design
• Performance trade-offs: electrical, mechanical, thermal management (air, liquid cooling)

System designers must resolve a complex set of tradeoffs among package/board/backplane/cable design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

CFA topics of interest

• Design, architecture and/or SI analysis of complete backplane and cable interconnect systems
• Backplane and cable signal conditioning
• Copper-fiber trade-offs and common port design challenges
• Electrical-Optical-Electrical system designs, tradeoffs, and challenges for data center and AI/ML applications 
• System interconnect and switch fabric architecture
• Flex PCB and other advanced PCB design tradeoffs and challenges
• Design verification (validation) and correlation
• PCI Express, Gen 5/6/7, Ethernet, and other standard-based architectures
• Next-gen high-speed serial link standards/MSA, e.g. 224/448Gb/s, simultaneous bidirectional links
• IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
• Effects of adaptative equalization on link margins
• End-to-end link design, ideas, and algorithms that optimize link performance and latency while meeting reach and power requirements
• SerDes design architectures and their influence on link development
• PAM-N vs. NRZ vs. other advanced modulation schemes system trade-offs/case studies
• Serial link system performance evaluation techniques (e.g. COM, Salz SNR)
• AI/ML techniques for high-speed link design optimization

• 224/448Gb/s system design ideas and challenges (SerDes, package, PCB/Cable, modulation, coding) 
• PCI-Express Gen 6, 7, and 8 design ideas and challenges
• Signal integrity design ideas and challenges for automotive/HPC/AI/ML applications
• Challenges and ideas in adaptative equalization across vendors in real-world environment

High-speed serial system impairments caused by jitter, noise, distortion, crosstalk, and ISI, can translate into bit, symbol, and frame errors. This track covers techniques for reducing errors, BER/SER/FLR (bit/symbol/frame loss ratio) through analysis of measurements, simulations, and models of components, subsystems, and systems.

CFA topics of interest:

•  Electro/Optic measurement and modeling of data links
• ML/AI assisted measurement and simulation techniques
• Measurement and modeling for error ratio, signal-to-noise & distortion ratio (SNDR), effective return loss (ERL), ratio of level-mismatch (R_LM)/non-linearity and distortion analysis
• Expansion of penalty-based measurements, such as Transmitter Dispersion Eye Closure Penalty Quaternary (TDECQ) in optical to Electrical Eye Closure Quaternary (EECQ) in electrical
• Modeling, simulation, and measurements of correlated and uncorrelated jitter, noise, crosstalk, reflection, and inter-symbol interference (ISI)
• Correlation of performance between advanced model CTLE/FFE/DFE/MLSD based simulation and physical measurements of the systems
• Clock recovery and reference clock impact. Analysis of clocks in time/frequency/phase domains. Embedded/Common/Forward clocking methodologies
• Channel operating margin (COM) - applying COM to measurements
• PAM-n and QAM-n analysis, measurement and modeling for pre-FEC BER/SER and block error count associate with post-FEC BER/FLR minimization
• Standard compliance and requirements for measurement systems: bandwidth, noise floor, intrinsic jitter
• Stressed eye testing: Jitter and interference calibration, tolerance measurement, for FFE, DFE, MLSD
• Channel/test fixture de-embedding/embedding and modeling 

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, synchronization, timing, detection, and FEC methods. This track covers design, modeling, analysis, implementation, and validation of such techniques.

CFA topics of interest

• Power, latency and performance architectural trade-offs for emerging applications (AI/ML, 6G, HPC, etc.)
• AI/ML approaches for modulation, precoding, equalization, detection, code design/decoding
• Equalization, detection, FEC techniques for energy efficient interfaces (EEI): retimed optics (CDR/DSP), non-retimed linear optics (LPO), and co-packaged optics (CPO)
• Signal processing and equalization techniques for bi-directional links
• COM methodologies and optimization of reference architecture, equalization, and detection
• End-to-end channel analysis and compliance methodology
• Signal detection algorithms such as maximum likelihood sequence detection (MLSD)/decision feedback equalization (DFE)
• Advanced modulation and coding (e.g. PAM-n, QAM/coherent, Trellis Coded Modulation (TCM), concatenated code, etc.)
• FEC (forward error correction), error bursts/propagation, frame error rate (FER) analysis, modeling and implementation
• FEC encoder and decoder algorithms, hard/soft detection and decoding
• FEC techniques and analysis related to coding layers (e.g. Ethernet PCS/PMA)
• Signal processing and related modeling for optical links, components, circuits, and noise sources
• Equalization techniques for high-speed serial links
• Adaptive equalization and tap optimization
• Back-channel training methods and performance
• CDR and PLL algorithms, modeling, and realization
• Carrier synchronization for coherent and light-weight coherent systems
• Lab validation of system performance and architecture choices
• SerDes device simulation (e.g. simulation of signal path and algorithms)
• Correlating simulation and measurement
• Pseudo random and stress test data patterns and code frequency spectra
• Signal coding, scrambling and DC balance modeling

Panel and tutorial topics of interest

• Joint optical and electrical link modeling and performance
• The future of copper versus optical communication at the board level
• AI applied to high-speed signal processing, equalization, and FEC

Power Integrity (PI), distribution, and management are essential for system functionality and performance. This track addresses system-level power distribution network design, modeling, and analysis on boards, packages, and chips, including thermal and reliability considerations ? - in HPC, AI, and ML applications, for instance. It emphasizes the modeling and analysis of impedance, supply noise, and/or power induced jitter, and their impact on overall system performance.

CFA topics of interest

• System supply design
  • DC-DC converter, VRD and VRM design including GaN, SIC, and module technologies
  • Dynamic response and control loop design and performance
  • Current sharing and voltage distribution in multiphase regulation
  • Power efficiency management strategies
  • Power-aware architecture
  • Power modes management for portable and mobile electronics
  • Low-voltage, high-power designs
  • VRM, VRD, and DC-DC converter modeling and simulation
  •  EMC and SI/PI impact of AC-DC converters on-board, modules, and data centers
  • PMIC and its impact on PDN noise and power induced jitter
  • PDN optimization with PMIC
• Chip-level power distribution and regulation impact on system PDN performance
  • On-chip power grid inductance, resistance, and on-die decoupling
  • Dynamic and static voltage variations
  • On-chip regulator and power gating impact on power integrity
• System level PDN design strategy
  • HPC, EV, AI, and ML applications
  • Chip/package/board analysis and decoupling optimization
  • PDN performance vs. cost, size, yield, reliability, etc.
  • System and PCB PDN modeling and simulation
  • PDN specifications, measurements, and correlation
  • System power noise and transients measurement, modeling and mitigation
  • Electro-thermal analysis and reliability
  • Power-induced crosstalk
  • Vertical power integration and vertical power delivery
  • Very high current PDN design and validation

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMC/EMI issues. This track raises awareness and the impact for design and systems engineers involved in circuit architecture, supply designs, harnesses, headers, cables, and PCB interface performance in automotive design platforms. It includes power distribution network design effects, modeling and analysis of boards, packages, and chips in order to mitigate possible EMC failures and improve products in the early design stages.

CFA topics of interest

• Design techniques to reduce or eliminate sources of EMI
• Near-field and far-field radiation computations and scan
• Pre- and post-qualification testing for EMC emissions
• EMI radiation and suppression in automotive designs
• EMI system susceptibility to noise
• Electromagnetic analysis of radiating structures
• Near-field coupling and system crosstalk
• Emissions and interference modeling
• RFI/de-sense and co-existence for mobile electronic devices
• Noise characterization and containment
• EMI troubleshooting techniques
• Impact of cable harness in automotive platforms
• Pre-qualification testing for immunity (radiated, ESD, etc.)
• Shielding at PCB, package, and system level
• EMI measurements and measurement techniques
• New shielding techniques and novel shielding materials
• Meeting compliance requirements
• AI and machine learning for EMC measurement systems
• Power supply consideration and noise effects for EMI/RFI
• Effect of power delivery systems on EMC performance
• Signal and power optimization for reducing emissions
• Effects of mode conversion on system performance
• EMI for high-density multi-port systems
• ESD modeling and measurements

Tutorial topic of interest

• EMC root-cause for failure analysis
• EMC analysis, simulations and measurements
• Locating and fixing EMI problems in PCB areas
• EMC design ideas and challenges for automotive applications

Advancements in measurement techniques are constantly being made for all aspects of signal and power integrity. This track focuses on the new techniques with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

CFA topics of interest

• Measurement Methods for SI, PI, and EMI/EMC
  • Classic measurements with modern instruments i.e., capturing a PRBS data pattern with picosecond UIs
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Power supply noise measurement methods for dynamic load response, ripple injection, very low impedences, etc.
  • Reference planes, partial S-parameters, behavioral models, as-fabricated, etc.
  • Measurement methods for error ratio, signal-to-noise & distortion ratio (SNDR), effective return loss (ERL), ratio of level-mismatch (RLM), stressed eye distortion, power spectral density, etc.
  • Measurement methods at extreme temperatures
• ATE and Multi-port Test Systems
  • ATE and sub-systems design validation and production at speed testing
  • ATE test sockets and multi-port switch matrix systems
  • Built in self-test methods with AI technology
• Hardware Technology and Architecture
  • Evolution of network analyzers, oscilloscopes, spectrum analyzers, sources, etc.
  • One box does it all vs. traditional instruments vs. custom measurement systems
  • Machine learning for measurement systems
• Application Specific Measurements for Emerging Technologies
  • Measurement methods for compliance with standards
  • Inter-pair skew for low latency in 5G, 6G, AI processing, etc.
  • Extreme environments such as automotive and quantum
  • PI challenges with GaN for low-power IoT, medical, consumer products, etc.
• Fixture Design and De-embedding
  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
  • IEEE and IPC standards for fixture mitigation and material properties measurements
  • Fixture de-embedding techniques including EM-solver and measure-based models
  • Mixed standard calibration methods for non-coaxial reference planes
  • Comparing calibration methodologies: uncertainty and residual error of calibration methods
  • S-parameter quality, causality, and passivity of measured data
  • Relationships between time domain and frequency domain measurements

Panel topic of interest:

• How much measurement bandwidth is required

Modeling of signals on interconnects with high data rates often requires use or extension of electromagnetic (EM) analysis techniques. This track includes passive link analysis and optimization for industry standards (28G, 100G, 400G, 800G, PCIE, USB, SATA, DDR, UCIe) with the use of electromagnetic and microwave signal integrity analysis techniques as well as validation with measurements.

CFA topics of interest

• Signal integrity analysis with RF/microwave techniques
• Electromagnetic analysis of interconnects
• Interconnect analysis validation with measurements
• S-parameters in analysis of broadband interconnect systems
• Analysis of losses, dispersion, coupling, cross talk, and mode conversion in interconnects
• Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
• Electromagnetic modeling of channels including PCB traces, vias, packages, cables, fiber weave effects, and connectors
• Simulation modeling and analysis of interaction between power distribution networks and signal interconnects
• Via and via array design and optimization including BGAs and pin fields
• Analysis dealing with competing impedance specifications vs. channel modeling issues
• Packages, chiplets, and interposer interconnect design and optimization
• PCB and package material modeling and identification for EM analysis

Machine-learning algorithms can efficiently derive models for electronics and system design automation and enable fast, accurate design and verification of microelectronic circuits and systems. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. Machine learned generative models cover the entire solution space vs. tradition-discriminative models. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

CFA topics of interest

• Static and dynamic neural network models for high-speed channels and SerDes
• Channel and SerDes performance optimization using PCA generative models
• ML and DoE techniques for optimizing designs with numerous parameter options
• Generative and Bayesian surrogate models for response surface approximation
• Early predictive models for design planning
• Machine learning for proactive hardware failure predictions
• Supervised and un-supervised deep learning for hardware system performance tuning
• ML techniques for improved rational function model extraction from S-parameters
• GPU/TPU accelerated SerDes and channel simulation
• Automated high-speed PCB layout design using deep learning
• ML model portability & reusability across tools and tool flows
• Training and inference tradeoffs for speed and accuracy
• AI/ML assisted design for SI/PI for single-multi die, interposer & packaging
• AI/ML assisted design for EMC
• AI/ML assisted design for thermal analysis
• ML and AI techniques for fast measurement adaptation/optimization, device characterization, and Design for everything (DFX)
• Digital twins for real-time dynamic performance optimization
• Large language models and Gen AI for SI/PI
• Future proofing AI models techniques such as fine tuning and transfer learning