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DesignCon Best Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation. The awards serve to acknowledge the authors who receive them as leading practitioners in semiconductor and electronic design. The awards also provide incentive to authors to produce high-quality DesignCon papers and present them in a lucid and compelling manner.
DesignCon Best Paper Awards recipients are selected through a two-step process. The first step is a review of the full-length papers accepted for the current year's program. Members of the DesignCon Technical Program Committee rank these papers based on quality, relevance, impact, originality, and lack of commercial content, which determines the finalists. While selection as a finalist for a DesignCon Best Paper Awards is a notable achievement in itself, winners are then chosen from the finalists based on the quality of their presentations as judged by attendee feedback collected during the conference.
An additional “Early-Career Best Paper Award” was introduced in 2020. The goal of this new award is to encourage and recognize excellence in the challenging task of creating a technical paper. Papers where the lead author has a maximum of seven years of professional experience are nominated as finalists, and one is chosen as the Early-Career Best Paper Award winner based on attendee ratings of the presentations.
2023 Best Paper Award Winners and Early-Career Best Paper Award Winner
3D Connection Artifacts in PDN Measurements
Ethan Koether, Amazon
Kristoffer Skytte, Cadence
John Phillips, Cadence
Shirin Farrahi, Cadence
Joseph Hartman, Oracle
Sammy Hindi, Ampere Computing Inc
Mario Rotigni, STMicroelectronics
Gustavo Blando, Samtec
Istvan Novak, Samtec
Data-Driven PAM4 SerDes Modeling with Generative Adversarial Network
Yongjin Choi, Hewlett Packard Enterprise
Priyank Kashyap, North Carolina State University
Wenzhen (Shawn) Sun, Tektronix
Muhammad Saad Chughtai, Tektronix
Chris Cheng, Hewlett Packard Enterprise
Pual Franzon, North Carolina State University
Designing the Best Reference Transmitter for Serdes Testing: AWG vs BERT
Stefan Moosburger, BitifEye
Anton Unakafov, BitifEye
Alexander Schmitt, BitifEye
Julien Henaut, BitifEye
Afshin Attarzadeh, BitifEye
Ransom Stephens, Ransom’s Notes
Finite Element Modelling of Copper Foil Loss from AFM Measurements
Yanice Baidouri, Circuit Foil
Benoît Wittmann, Circuit Foil
How to Design Secured Power Delivery Network (PDN)of Cryptographic Devices: Challenges, Evaluation Methods, and Solutions
Youngwoo Kim, NAIST/JST CREST/ Sejong University
Fujimoto Daisuke, NAIST/ JST CREST
Shinpei Wada, NAIST
Taiki Kitazawa, NAIST
Yuichi Hayashi, NAIST/ JST CREST
Noise in Traffic: Signal Emulation for Automotive Apps
Yash Pathak, BitifEye
Parthasarathy Raju, BitifEye
Valentina Unakafova, BitifEye
Anton Unakafov, BitifEye
Julien Henaut, BitifEye
Kevin Kershner, Keysight
Alexander Schmitt, BitifEye
Ransom Stephens, BitifEye
Rigorous Correlation Methodology for PCIe Gen5 & Gen6 DSP Based IBIS-AMI Models
Adrien Auge, Alphawave Semi
Michael Klempa, Alphawave Semi
Statistical BER Analysis of Concatenated FEC in Multi-Part Links
Richard Barrie, University of Toronto
Ming Yang, University of Toronto/Alphawave SEMI
Anthony Chan Carusone, University of Toronto/Alphawave SEMI
2023 Early-Career Best Paper Award Winner
Data-Efficient Supervised Machine Learning Technique for Practical PCB Noise Decoupling
Morten Schierholz, Hamburg University of Technology
Ihsan Erdin, Celestica Inc.
Jayaprakash Balachandran, Cisco Inc.
Christian Schuster, Hamburg University of Technology
2022 Best Paper Award Winners and Early-Career Best Paper Award Winner
224Gbps-PAM4 End-to-End Channel Solutions for High-Density Networking System
Jenny Xiaohong Jiang, Intel Corporation
Mike Peng Li, Intel Corporation
Ed Milligan, Intel Corporation
Yee Lun Ong, Intel Corporation
John Medina, Intel Corporation
Qian Ding, Intel Corporation
Hsinho Wu, Intel Corporation
Masashi Shimanouchi, Intel Corporation
Kemal Aygun, Intel Corporation
Stas Litski, Intel Corporation
Sandeep Mada, Intel Corporation
A New Challenge for Neuromorphic Computing Systems: From Off-chip Interconnects to On-chip Interconnects
Taein Shin, KAIST
Hyunwook Park, KAIST
Seongguk Kim, KAIST
Keunwoo Kim, KAIST
Keeyoung Son, KAIST
Joungho Kim, KAIST
A Processing-In-Memory on High Bandwidth Memory (PIM-HBM): Impact of Interconnect Channels on System Performance in 2.5D/3D IC
Seongguk Kim, KAIST
Hyunwook Park, KAIST
Taein Shin, KAIST
Daehwan Lho, KAIST
Keeyoung Son, KAIST
Keunwoo Kim, KAIST
Minsu Kim, KAIST
Joonsang Park, KAIST
Joungho Kim, KAIST
Current Limitation and New Method to Accurately Estimate Reference Signal Jitter for 100+ Gbps 802.3 and OIF/CEI Interference Tolerance Test
Masashi Shimanouchi, Intel Corporation
Mike Peng Li, Intel Corporation
Hsinho Wu, Intel Corporation
Deep Reinforcement Learning-based Channel Flexible Equalization Scheme: An Application to High Bandwidth Memory
Seonguk Choi, KAIST
Minsu Kim, KAIST
Hyunwook Park, KAIST
Haeyeon Rachel Kim, KAIST
Joonsang Park, KAIST
Jihun Kim, KAIST
Keunwoo Kim, KAIST
Daehwan Lho, KAIST
Jiwon Yoon, KAIST
Jinwook Song, Samsung Electronics
Kyungsuk Kim, Samsung Electronics
Jonggyu Park, Samsung Electronics
Joungho Kim, KAIST
IBIS-AMI Modeling and Correlation Methodology for ADC-Based SerDes Beyond 100 Gb/s
Aleksey Tyshchenko, SeriaLink Systems
David Halupka, SeriaLink Systems
Richard Allred, MathWorks
Tripp Worrell, MathWorks
Barry Katz, MathWorks
Clinton Walker, Alphawave IP
Adrien Auge, Alphawave IP
Imitate Expert Policy and Learn Beyond: A Practical PDN Optimizer by Imitation Learning
Haeyeon Rachel Kim, KAIST
Minsu Kim, KAIST
Sungwook Choi, KAIST
Jihoon Kim, KAIST
Junsang Park, KAIST
Keeyoung Son, KAIST
Hyunwook Park, KAIST
Subin Kim, Samsung Global Technology Research (GTR)
Joungho Kim, KAIST
Proper Ground Return Via Placement for 40+ Gbps Signaling
Michael Steinberger, MathWorks
Donald Telian, SiGuys
Michael Tsuk, MathWorks
Vishwanath Iyer, MathWorks
Janakinadh Yanamadala, MathWorks
2022 Early-Career Best Paper Award Winner
Integration-based Method for Surface Roughness Modeling of Copper Foils
Yuanzhuo Liu, Missouri University of Science and Technology
Yuandong Guo, Missouri University of Science and Technology
Chaofeng Li, Missouri University of Science and Technology
Xiaoning Ye, Intel Corporation
Kim DongHyun, Missouri University of Science and Technology
2021 Best Paper Award Winners and Early-Career Best Paper Award Winner
A Case Study in the Development of a 112 Gbps-PAM4 Silicon & Connector Test Platform
Jean-Remy Bonnefoy, Samtec
Ted Ballou, Samtec
Istvan Novak, Samtec
Gustavo Blando, Samtec
Scott McMorrow, Samtec
Raj Mahadevan, Alphawave IP
Cost Effective Power Integrity Methodology for Integrating Next-Generation High-Speed Ips
Raj Mohan Mondal, Intel Corp.
Praveen B. Pai, Intel Corp.
Ashwini Anil Kumar, Intel Corp.
Vishram S. Pandit, Intel Corp.
Kinger Cai, Intel Corp.
End-to-end IBIS-AMI Modeling & Simulations of Electrical/Optical Links
Qing Xu, Ranovus Inc.
Hongtao Zhang, Xilinx Inc.
Jackson Klein, Ranovus Inc.
James Whiteaway, Ranovus Inc.
Simon Gebrewold, Ranovus Inc.
Claus Dorschky, Ranovus Inc.
Mike Koehler, Ranovus Inc.
Dylan Logan, Ranovus Inc.
Christoph Schulien, Ranovus Inc.
Hojjat Salemi, Ranovus Inc.
Jeff Hutchins, Ranovus Inc.
Georg Roell, Ranovus Inc.
Yohan Frans, Xilinx Inc.
Geoff Zhang, Xilinx Inc.
From Simulation to Production: An In-Depth Look at Designing & Productizing GDDR6x, the World’s First PAM-4 Memory Interface
Sunil Sudhakaran, NVIDIA
Tim Hollis, Micron Technology, Inc.
Arash Zargaran-Yazd, NVIDIA
Zuhaib Sheikh, NVIDIA
Daniel Lin, NVIDIA
Baal Yang, NVIDIA
Russell Newcomb, NVIDIA
Gautam Bhatia, NVIDIA
Robert Bloemer, NVIDIA
Virendra Kumar, NVIDIA
Yujeong Shim, Google
Ronny Schneider, Micron Semiconductor
Mani Balakrishnan, Micron Semiconductor
Maksim Kuzmenka, Micron Semiconductor
David Ovard, Micron Technology, Inc.
Global Optimization of Wireline Transceivers for Minimum Post-FEC vs. Pre-FEC BER
Ming Yang, University of Toronto
Shayan Shahramian*, Huawei Canada
Henry Wong, Huawei Canada
Peter Krotnev, Huawei Canada
Anthony Chan Carusone, University of Toronto
*Now with Alphawave IP
Holistic Power Supply Induced Jitter Accumulation Response Surface Modeling for HBM Chiplet Interconnect System
Hing “Thomas” To, Xilinx Inc.
Nitin Srivastava, Xilinx Inc.
Ajay Kumar Sharma, Xilinx Inc.
Wui Hung “Eric” Moo, Xilinx Inc.
Changyi Su, Xilinx Inc.
Juan Wang, Xilinx Inc.
Innovative Designs for Optimizing 112G+ BGA Fan-Out & Connector Footprint Crosstalk
Jinlong Li, ZTE
Cherie Chen, TE
Peng Zach, TE
Bi Yi, ZTE
Zhongmin Wei, ZTE
Yu Bi, ZTE
Neural Language Model Enables Extremely Fast & Robust Routing on Interposer
Minsu Kim, KAIST
Hyunwook Park, KAIST
Seonguk Choi, KAIST
Haeyeon Rachel Kim, KAIST
Seongguk Kim, KAIST
Keeyoung Son, KAIST
Keunwoo Kim, KAIST
Daehwan Lho, KAIST
Kyunjune Son, KAIST
Subin Kim, Samsung Electronics
Joungho Kim, KAIST
SNDR Analysis & Its Impacts on Link Performance
Hsinho Wu, Intel Corp.
Marianne Nourzad, Intel Corp.
Zuoguo Wu, Intel Corp.
John Y. Yang, Intel Corp.
Xiaoshu Zhao, Intel Corp.
Masashi Shimanouchi, Intel Corp.
Mike Li, Intel Corp.
2021 Early-Career Best Paper Award Winner
Analysis of Electro-Static Discharge to Through-Silicon Via
Zhekun Peng, Missouri University of Science and Technology
Wei Zhang, Missouri University of Science and Technology
DongHyun Kim, Missouri University of Science and Technology
2020 Best Paper Award Winners and Early-Career Best Paper Award Winner
Chip-Level Design
Real Time On-Die Power & Thermal Profiling for Machine Learning Design Applications
Hing "Thomas" To, Xilinx Inc.
Nitin Srivastava, Xilinx Inc.
Ajay Kumar Sharma, Xilinx Inc.
Wui Hung "Eric" Moo, Xilinx Inc.
Changyi Su, Xilinx Inc.
Juan Wang, Xilinx Inc.
Ed C. Priest, Xilinx Inc.
Accurate IBIS-AMI modelling of DSP-Based 56G Ethernet Transceivers & Successful Hardware to Model Correlation
Priyank Shukla, Synopsys
Kevin (Kai) Li, Synopsys
Ayal Shoval, Synopsys
Ismael Duron Rosales, Synopsys
Board/System-Level Design
Industry-Leading High Bandwidth Memory Interface Solutions for Inference/AI
Billy Koo, SAMSUNG Electronic
Soo-Min Lee, SAMSUNG Electronics
Kwanyeob Chae, SAMSUNG Electronics
Juyoung Kim, SAMSUNG Electronics
Accurate Simulation & Measurement Correlation of Power Supply Noise Coupling & Induced Jitter for High-Speed SerDes
Xiaoping Liu, Intel Corporation
Wendem Beyene, Intel Corporation
Jihong Ren, Intel Corporation
Shiva Prasad Kotagiri, Intel Corporation
Joseph Kho Boon Hock, Intel Corporation
Chor Kuen Yeow, Intel Corporation
Dong-Myung Choi, Intel Corporation
Self-Evolution Cascade Deep Learning for SerDes Adaptive Equalization
Bowen Li, Xilinx Inc.
Brandon Jiao, Xilinx Inc.
Chih-Hsun Chou, Xilinx Inc.
Romi Mayder, Xilinx Inc.
Paul Franzon, North Carolina State University
Geoffrey Zhang, Xilinx Inc.
Serial Link Design
Signal Integrity Characterization of Via Stubs on High Speed DDR4 Channels
Benjamin Dannan, Diversey Inc.
End-to-end FEC Performance Analysis for Multi-Part PAM4 Systems
Xiaoqing (Amanda) Dong, Xilinx Inc.
Chunxing (Nick) Huang, Zhongzeling Electronics
Geoff (Geoffrey) Zhang, Xilinx Inc.
Power & RF Design
Current Distribution, Resistance & Inductance in Power Connectors
Adam Gregory, Samtec
Clement Luk, Samtec
Gary Biddle, Samtec
Gustavo Blando, Samtec
Istvan Novak, Samtec
System Level Radiated Emission Mitigation at High Frequencies when Other Methods are Not Effective Enough
Ali Khoshniat, Santa Clara University
Ramesh Abhari, Santa Clara University
Analysis on Power Via Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk
DongHyun Kim, Missouri University of Science and Technology
Siqi Bai, Missouri University of Science and Technology
Jongjoo Lee, Missouri University of Science and Technology
Junda Wang, Missouri University of Science and Technology
Jun Wang, Missouri University of Science and Technology
Junyong Park, Missouri University of Science and Technology
Bichen Chen, Facebook, Inc.
Xu Wang, Facebook, Inc.
Srinivas Venkataraman, Facebook, Inc.
Jun Fan, Missouri University of Science and Technology
2020 Early-Career Best Paper Award Winner
Optimized Wireless System Design with Minimal RFI Using Antenna Near Field Approach
Deepak Pai Hosadurga, Amazon Lab 126
Qiaolei Huang, Amazon Lab 126
Akshay Mohan, Amazon Lab 126
Jagan Rajagopalan, Amazon Lab 126
2019 Best Paper Award Winners
Chip-Level Design
Simulation & Measurement Correlation of Power Supply Noise Induced Jitter for Core & Digital IP Blocks
Hyo-Soon Kang, Intel Corporation
Guang Chen, Intel Corporation
Ashkan Hashemi, Intel Corporation
Wern Shin Choo, Intel Corporation
David Greenhill, Intel Corporation
Wendem Beyene, Intel Corporation
Top-Down Jitter Specification Approach for HBM System Optimization
Hing “Thomas” To, Xilinx Inc.
Nanju Na, Xilinx Inc.
Anna Wong, Xilinx Inc.
Haixin Ke, Xilinx Inc.
Ajay Kumar Sharma, Xilinx Inc.
Wui Hung Moo, Xilinx Inc.
A Review of Combiner/Divider PCB Design Topologies for 5G & WiGig ATE Applications
Giovani Bianchi, Advantest
José Moreira, Advantest
Alexander Quint, Kalrsruhe Institute für Technologie
Board/System-Level Design
PCB Interconnect Modeling Demystified
Lambert (Bert) Simonovich, Lamsim Enterprises Inc.
Serial Link Design
A Methodology for Performance Comparison of Center & Edge Sampling in Serial Links
Hossein Shakiba, Huawei Canada – HiLink
Shayan Shahramian, Huawei Canada – HiLink
Behzad Dehlaghi, Huawei Canada – HiLink
David Cassan, Huawei Canada – HiLink
Davide Tonietto, Huawei Canada – HiLink
100+ Gb/s Ethernet Forward Error Correction (FEC) Analysis
Cathy Ye Liu, Broadcom Inc.
Power & RF Design
A Fast & Simple RFI Mitigation Method without Compromising Signal Integrity
Qiaolei Huang, Missouri University of Science and Technology
Ling Zhang, Missouri University of Science and Technology
Yang Zhong, Missouri University of Science and Technology
Jagan Rajagopalan, Amazon Lab126
Deepak Pai, Amazon Lab126
Chen Chen, Amazon Lab126
Amit Gaikwad, Amazon Lab126
Chulsoon Hwang, Missouri University of Science and Technology
Jun Fan, Missouri University of Science and Technology
Using Multiple Huygens’ Boxes to Detect & Quantify the Coupling Path from Noise Source to Victim
Antonio Ciccomancini Scogna, Futurewei Technologies Inc.
Jiangqi He, Futurewei Technologies Inc.
Cheng Wei Chang, Huawei
Liu Chen Jun, Huawei
How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements
Istvan Novak, Samtec
Jim Nadolny, Samtec
Gary Biddle, Samtec
Ethan Koether, Oracle
Demistyfying Edge Launch Connectors
Raul Stavoli, Carlisle IT
Davi Correia, Carlisle IT
Emad Soubh, Carlisle IT
2018 Best Paper Award Winners
Board/System-Level Design
16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory
Tim Hollis, Micron Technology
Salman Jiva, Micron Semiconductor Products
Martin Brox, Micron Semiconductor
Wolfgang Spirkl, Micron Semiconductor
Thomas Hein, Micron Semiconductor
Dave Ovard, Micron Technology
Roy Greeff, Micron Technology
Dan Lin, Micron Technology
Michael Richter, Micron Semiconductor
Peter Mayer, Micron Semiconductor
Walt Moden, Micron Technology
Maksim Kuzmenka, Micron Semiconductor
Mani Balakrishnan, Micron Semiconductor
Milena Ivanov, Micron Semiconductor
Manfred Plan, Micron Semiconductor
Marcos Alvarez Gonzalez, Micron Semiconductor
Bryce Gardiner, Micron Technology
Dong Soon Lim, Micron Technology
Statistical-Based RE DCD Jitter Analysis in High Speed NAND Flash Memory
Sayed Mobin, Western Digital
Cindy Cui, Keysight Technologies
Serial-Link Design
A Study of Forward Error Correction Codes for SAS Channel
Haitao (Tony) Xia, Broadcom Ltd
Haotian Zhang, Broadcom Ltd
Aravind Nayak, Broadcom Ltd
Bruce Wilson, Broadcom Ltd
Jun Yao, Etopus
Effective Link Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial Links at 112 Gbps and Beyond
Hsinho Wu, Intel Corporation
Masashi Shimanouchi, Intel Corporation
Mike Peng Li, Intel Corporation
Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and Implications for COM
Torsten Reuschel, Hamburg University of Technology
Ömer Yildiz, Hamburg University of Technology
Jayaprakash Balachandran, Cisco Systems Inc.
Cristian Filip, Mentor Graphics
Nitin Bhagwath, Mentor Graphics
Bidyut Sen, Cisco Systems Inc.
Christian Schuster, Hamburg University of Technology
Feedforward Equalizer Location Study for High Speed Serial Systems
Kevin Zheng, Stanford University
Boris Murmann, Stanford University
Hongtao Zhang, Xilinx
Geoff Zhang, Xilinx
Power & RF Design
40 GHz PCB Interconnect Validation: Expectations vs Reality
Marko Marin, Infinera
Yuriy Shlepnev, Simberian
A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics
Vladimir Dmitriev-Zdorov, Mentor Graphics
Bert Simonovich, Lamsim Enterprises
Igor Kochikov, Mentor Graphics
A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics
Heidi Barnes, Keysight Technologies
Eric Bogatin, Teledyne LeCroy
José Moreira, Advantest
Jason Ellison, The Siemon Company
Jim Nadolny, Samtec
Ching-Chao Huang, Ataitec
Mikheil Tsiklauri, Missouri University of Science and Technology
Se-Jung Moon, Intel Corporation
Volker Herrmann, Rohde and Schwarz
Accurate and Fast RFI Prediction Based on Dipole Moment Sources and Reciprocity
Qiaolei Huang, Missouri University of Science and Technology
Takashi Enomoto, Sony Global Manufacturing and Operations
Shingo Seto, Sony Global Manufacturing and Operations
Kenji Araki, Sony Global Manufacturing and Operations
Jun Fan, Missouri University of Science and Technology
Chulsoon Hwang, Missouri University of Science and Technology
2017 Best Paper Award Winners
Chip-Level Design
Characterizing and Selecting the VRM
Steve Sandler, Picotest
Board/System-Level Design
FastBER: A Novel Statistical Method for Arbitrary Transmitter Jitter
Yunhui Chu, Intel Corporation
Alaeddin Aydiner, Intel Corporation
Kai Xiao, Intel Corporation
Beomtaek Lee, Intel Corporation
Dan Oh, Samsung Electronics
Oleg Mikulchenko, Intel Corporation
Adam Norman, Intel Corporation
Rob Friar, Intel Corporation
Charles Phares, Intel Corporation
Non-Destructive Analysis and EM Model Tuning of PCB Signal Traces using the Beatty Standard
Heidi Barnes, Keysight Technologies
José Moreira, Advantest
Manuel Walz, Advantest
RX IBIS-AMI Model Silicon Correlation Metrics and Model Development Methodology
Masashi Shimanouchi, Intel Corporation
Hsinho Wu, Intel Corporation
Mike Peng Li, Intel Corporation
Serial Link Design
Exploring Efficient Variability-Aware Analysis Method for High-Speed Digital Link Design Using PCE
Jan B. Preibisch, Technische Universität Hamburg-Harburg
Torsten Reuschel, Technische Universität Hamburg-Harburg
Katharina Scharff, Technische Universität Hamburg-Harburg
Jayaprakash Balachandran, Cisco Systems Inc.
Bidyut Sen, Cisco Systems Inc.
Christian Schuster, Technische Universität Hamburg-Harburg
Investigation of Mueller-Muller CDR Algorithms in PAM4 High speed Serial Links
Yuhan Yao, Oracle Corporation
Xun Zhang, Oracle Corporation
Dawei Huang, Oracle Corporation
Jianghui Su, Oracle Corporation
Muthukumar Vairavan, Oracle Corporation
Chai Palusa, Oracle Corporation
PCIe Gen4 Standards Margin Assisted Outer Layer Equalization for Cross Lane Optimization in a 16GT/s PCIe Link
Mohammad S. Mobin, Broadcom Ltd
Haitao Xia, Broadcom Ltd
Aravind Nayak, Broadcom Ltd
Gene Saghi, Broadcom Ltd
Christopher Abel, Broadcom Ltd
Lane Smith, Broadcom Ltd
Jun Yao, Broadcom Ltd
Power & RF Design
Cost-effective PCB Material Characterization for High-volume Production Monitoring
Yongjin Choi, Hewlett-Packard Enterprise
Christopher Cheng, Hewlett-Packard Enterprise
Yasin Damgaci, Hewlett-Packard Enterprise
Nagaraj Godishala, Hewlett-Packard Enterprise
Yuriy Shlepnev, Simberian
Overview and Comparison of Power Converter Stability Metrics
Joseph ‘Abe’ Hartman, Oracle
Alejandro 'Alex' Miranda, Oracle
Kavitha Narayandass, Oracle
Alexander Nosovitski, Oracle
Istvan Novak, Oracle
RFI and Receiver Sensitivity Analysis in Mobile Electronic Devices
Antonio Ciccomancini Scogna, Samsung Electronics Mobile Division, HE Group
Hwanwoo Shim, Samsung Electronics Mobile Division, HE Group
Jiheon Yu, Samsung Electronics Mobile Division, HE Group
Chang-Yong Oh, Samsung Electronics Mobile Division, HE Group
Seyoon Cheon, Samsung Electronics Mobile Division, HE Group
NamSeok Oh, Samsung Electronics Mobile Division, HE Group
Dong Sub Kim, Samsung Electronics Mobile Division, HE Group
2016 Best Paper Award Winners
High-Speed Signal Design
A Versatile Spectrum Shaping Scheme for Communicating Beyond Notches in Multi-Drop Interfaces
Ali Hormati, Kandou Bus, Switzerland
Armin Tajalli, Kandou Bus, Switzerland
Christoph Walter, Kandou Bus, Switzerland
Kiarash Gharibdoust, EPFL, Switzerland
Amin Shokrollahi, Kandou Bus, Switzerland
Mid-Frequency Noise Coupling Between DC-DC Converters and High-Speed Signals
Laura Kocubinski, Oracle
Gustavo Blando, Oracle
Istvan Novak, Oracle
Memory & Parallel Interfaces
Analysis and Verification of DDR3/DDR4 Board Channel Impact on Clock Duty-Cycle-Distortion (DCD)
GaWon Kim, Altera
June Feng, Altera
Marjan Mokhtaari, Altera
David Lieby, Altera
Janmejay Adhyaru, Altera
Balaji Natarajan, Altera
Dan Oh, Altera
Optimal DDR4 System with Data Bus Inversion Feature in FPGA High Speed High Bandwidth Memory Interface
Thomas To, Xilinx
Changyi Su, Xilinx
Juan Wang, Xilinx
Penglin Niu, Xilinx
Yong Wang, Xilinx
Test & Measurement
Jitter, Noise Analysis and BER Synthesis on PAM4 Signals on 400 Gbps Communication Links
Maria Agoston, Tektronix
Mark L. Guenther, Tektronix
Richard J. Poulo, Tektronix
Kalev Sepp, Tektronix
Pavel Zivny, Tektronix
BER- and COM-Way Channel Compliance Evaluation: What are the Sources of Difference?
Vladimir Dmitriev-Zdorov, Mentor Graphics
Cristian Filip, Mentor Graphics
Chuck Ferry, Mentor Graphics
Alfred P. Neves, WildRiver Technology
A New Characterization Technique for Glass Weave Skew Sensitivity
Eric Bogatin, Teledyne LeCroy
Bill Hargin, Nan Ya Plastics
Vinit Sonawane, Univ. of Colorado, Boulder
Sanket Sapre, Univ. of Colorado, Boulder
Vidyadhar Yashwant Deodhar, Univ. of Colorado, Boulder
Nikhil Joshi, Univ. of Colorado, Boulder
Anand Ursekar, Univ. of Colorado, Boulder
Power Integrity
Impacts of Dynamic Noise in Multi-Core or SOC Designs
Yujeong Shim, Altera
Dan Oh, Altera
Electrical and Thermal Consequences of Non-Flat Impedance Profiles
Jae Young Choi, Oracle
Ethan Koether, Oracle
Istvan Novak, Oracle
Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices
Jin-Sung Youn, Samsung Electronics
Jieun Park, Samsung Electronics
Jinwon Kim, Samsung Electronics
Daehee Lee, Samsung Electronics
Sangnam Jeong, Samsung Electronics
Junho Lee, Samsung Electronics
Hyo-Soon Kang, Samsung Electronics
Chan-Seok Hwang, Samsung Electronics
Jong-Bae Lee, Samsung Electronics
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