Join us on our digital platform June 7-8, 2022, for education featuring new content plus encore presentations of select sessions recorded at DesignCon in April. View exhibitor profiles and connect with speakers, suppliers and other attendees.

If You Have Not Yet Registered: 
Click here to register.

If You Have Already Registered:
To access DesignCon’s digital offering, visit this page on June 7-8, and log in with the email address you used to register for the event. Information on how to use the Swapcard platform can be found here.

KEYNOTES

June 7, 2022

• 8-8:45 a.m. PDT
  The Realities of AI & Machine Learning: Cut Through the Hype & Move to Production
  Speaker: Laurence Moroney (Artificial Intelligence Lead, Google)
  Sponsored by: RAMBUS
  
• 1-1:45 p.m. PDT
  Progress Enabled: The Convergence of Photonic & Electronic ICs
  John Bowers (Fred Kavli Chair of Nanotechnology, University of California, Santa Barbara)

June 8, 2022

• 8-8:45 a.m. PDT
  Space Tech: Present & Future
  José Morey (Consultant, NASA, IBM, Hyperloop Transportation, Liberty BioSecurity Health and Technology)

PANELS

June 7, 2022

• 11:45 a.m.-1 p.m. PDT
  What is Needed for 224Gbps? System & Chip Vendors Perspective
  Moderator: Cathy Liu (Distinguished Engineer)
  Panelists: Pervez Aziz (Senior Principal Engineer, Nvidia), Broadcom Inc.), Pirooz Tooyserkani (Principal Engineer, Cisco Systems, Inc.), Srinivas Venkataraman (Signal Integrity Engineer, Facebook), Richard Ward (VP & GM of the Data Connectivity Group, Astera Labs Inc)

June 8, 2022

• 11 a.m.-12:15 p.m. PDT
  Modeling Passive Component for Power Integrity Simulations: How to Measure, How to Model, How to Use
  Moderator: Heidi Barnes (SI and PI Applications Engineer, Keysight Technologies)
  Panelists: Eric Bogatin (Professor, University of Colorado, Boulder), Jim DeLap (Electronics Product Manager, ANSYS), Joe Hock (Chief Scientist, R&D, Kyocera - AVX), Istvan Novak (Power Integrity Engineer, Samtec), Steve Sandler (Founder, Picotest.com)

CHIPHEAD THEATER SESSIONS

June 7, 2022

• 8:45-9:30 a.m. PDT
  Improving AR/VR Reality with 3D Time of Flight Sensing
  Speaker: Rolf Weber (Applications Engineer, Infineon Technology)
• 10:15-11:00 a.m. PDT
  New System-level Opportunities with OSFP-XD
  Speaker: Brian Kirk (CTO, High Speed Group, Amphenol)

June 8, 2022

• 8:45-9:30 a.m. PDT
  Production ML for Mission-Critical Applications
  Speaker: Robert Crowe (TensorFlow Developer Engineer, Google)
• 10:15-11 a.m. PDT
  Five Tips for Power Integrity Measurements on a Budget
  Speaker: Eric Bogatin (Professor, University of Colorado, Boulder)
• 12:15-1 p.m. PDT
  Limits of High-speed Connector & Cable Technology
  Speaker: Mick Felton (Director of Engineering, ACES)

OTHER

• Digital Expo Hall – Access to 130+ suppliers offering the latest technologies for your design projects.
• Networking – Ability to connect with speakers, suppliers, and other attendees online, and schedule meetings.
• Discount Code – A discount code to attend DesignCon’s annual in-person conference, January 31 – February 2, 2023, at the Santa Clara Convention Center.

All of the above plus these IEEE-accredited sessions:

Technical Sessions

June 7, 2022

• 8:45-9:30 a.m. PDT
  Validation of Achieving 200Gbps Signaling per Electrical Lane Over 1 Meter of Passive Twinaxial Copper Cable
  Speakers: Christopher DiMinico (President/CTO, MC Communications/PHY-SI LLC/SenTekse), Michael Klempa (Electrical Engineer, Amphenol ICC), David Nozadze (Signal Integrity Technical Leader, Cisco Systems), Michael Rowlands (SI Engineering Manager, Amphenol HSC)
• 9:30-10:15 a.m. PDT
  Generalized ccICN (Component Contribution Integrated Crosstalk Noise)
  Speaker: Se-Jung Moon (IO architect, Intel)
• 10:15-11 a.m. PDT
  Long-haul Inter-domain Power Noise
  Speakers: Ethan Koether (Power Integrity Engineer, Project Kuiper - Amazon), Istvan Novak (Power Integrity Engineer, Samtec), Mario Rotigni (Lead EMC Engineer for Automotive Microcontroller and SoC Team, STMicroelectronics)
• 11-11:45 a.m. PDT
  Next Generation 224Gbps-PAM4 SERDES, Channel & Link Systems
  Speaker: Mike Li (Fellow, Intel)
• 1-1:45 p.m. PDT
  Security Integrity Analytics by Thermal Side-channel Simulation: An ML-augmented Auto-POI Approach
  Speakers: Jimin Wen (Principal R&D Engineer, Ansys), Norman Chang (Ansys Fellow, Ansys), Hua Chen (R&D Engineer, Ansys), Jyh-Shing Roger Jang (Professor, National Taiwan University), Lang Lin (Lead Product Specialist, Ansys), David Luo (Graduate Student, National Taiwan University)
• 1:45-2:30 p.m. PDT
  Three Very Low-cost Technology Solutions for SI Applications
  Speaker: Eric Bogatin (Professor, University of Colorado, Boulder)

June 8, 2022

• 8:45-9:30 a.m. PDT
  Equalizer (TX/RX) Optimization at 112Gbps
  Speakers: Ryan Chodora (R&D Software Engineer, Keysight Technologies), Kalev Sepp (Senior Consultant, Sepson Analytics)
• 9:30-10:15 a.m. PDT
  Understanding the Effect of Temperature on Permittivity & Loss of Dielectric Substrates
  Speaker: Allen F. Horn III (Research Fellow, Rogers Corporation)
• 10:15-11 a.m. PDT
  Transient vs. Statistical: A Comparative Study on Practical Parallel Link Qualification Techniques
  Speaker: Ashkan Hashemi (Signal/Power Integrity Engineer, Amazon)
• 12:15-1 p.m. PDT
  224Gbps-PAM4 End-to-end Channel Solutions for High-density Networking System
  Speakers: Jenny Jiang (Principal Engineer, Intel), Mike Li (Intel Fellow, Intel)
• 1-1:45 p.m. PDT
  Optimization of a Co-packaged Laser Module Design Using Statistical Analysis for Signal Integrity
  Speaker: Junho Lee (Principal Electrical Engineer, Microsoft)