Casey Morrison is an accomplished system engineer with a record of developing innovative products and system level improvements to advance the industry. He actively engages with customers, industry peers, and technologists to enable seamless adoption of next-generation technologies in hardware designs. Casey has been involved in work to guide the industry through the changes and progression from 10-Gbps Ethernet to 800-Gbps Ethernet and 8-Gbps PCI Express (PCIe) to 32-Gbps Compute Express Link (CXL).
Casey first presented at DesignCon in 2013 when he collaborated with early adopters of 25-Gbps Ethernet. Since then, he has authored multiple white papers on 50G/100G PAM-4 technologies that discuss practical aspects of Signal Integrity including AC coupling capacitors, end-to-end system simulations, EMI issues and real-life considerations of Link Training just to name a few. Casey is actively involved in facilitating the transition of evolving Ethernet standards into high volume products.
As with Ethernet, Casey is a leading authority on PCI Express and Compute Express Link. At DesignCon 2020, Casey presented a step-by-step “how-to” guide for defining, executing, and analyzing system level simulations for PCIe 5.0 Root Complex, Retimer and End point. Casey is actively working with the industry to deploy CXL 2.0 solutions at scale.
Casey has received various industry recognitions during his career and is a recipient of the Raj Gupta System/Marketing Excellence award for being the top-performing engineer when he worked at Texas Instruments.