January 26–28, 2021

Santa Clara Convention Center, Santa Clara, CA

Bulk download for 2020 presentations are available for DesignCon 2020 conference pass holders.
*Please enter password provided on your conference badge.

Design Insights to Power Your Future

As the electronic industry surges ahead, so does the need for practical insights and solutions to engineer the next generation of products. Enter DesignCon. With technical paper sessions, panels, tutorials, and boot camps spanning 14 tracks, DesignCon’s three-day conference program provides the information you need to solve design challenges now and plan how to improve designs in the future.

Conference sessions cover all aspects of hardware design, including signal & power integrity, high-speed serial design, and machine learning. Sessions are provided for all levels of learning, with information for experienced engineers, recent graduates, and everyone in between.

Curated by our Technical Program Committee (TPC)—an expert panel of more than 90 industry professionals — the DesignCon curriculum is reviewed and updated each year to meet the needs of our ever-evolving industry. DesignCon sets the industry standard for education and technology conferences, offering today's mission-critical information for people designing tomorrow's electronics products.

Conference Tracks

Below is a description of each DesignCon 2021 track, along with sample topics. All relevant proposals—including topics other than those listed—will be considered

Select a track name for more details

Die, interposer, and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, packaging, and system interface levels. This includes SoC issues, multi-chip integration, power delivery networks, related noise, and jitter mitigation strategies.

Sample topics

  • Signal Integrity (SI), Power Integrity (PI), and Power Distribution Network (PDN) considerations in chip and packaging designs
  • Implications of interactions between chip-level and systems design decisions.
  • On-chip and chip-to-chip, chiplet, and chip to module (connector) interconnect design and analysis
  • 2.5D/3D interconnect and interposer design as applied to die/interposer/package technology
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-sequencing design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques to improve signal and power integrity
  •  Clock and reset strategies to improve signal and power integrity
  • Through-silicon vias (TSV)
  • System-in-Package (SiP) partition and IP integration
  • Design validation, correlation, and verification

Predicting critical aspects of system performance requires various analog and algorithmic modeling abstractions and simulation approaches. This track addresses the necessary challenges and solutions needed for that design and verification. Chip-to-chip data channels, clocks, and power solutions each have specialized modeling requirements that must be met to accurately predict system performance. Accurate IBIS and IBIS-AMI models, for example, should include full representation of the device’s features and benefits with full documentation of potential model limitations.

Sample topics

  • Serial channel modeling and analysis
    • IBIS-AMI model generation, validation, and simulation strategies
    • IBIS-AMI model quality and silicon correlation methodologies
    • Comparing COM versus IBIS-AMI modeling methods and analysis results
  • SI/PI modeling
    • Power-aware IBIS modeling for SSO simulation
    • Touchstone models for SI and Power
  • General modeling methodology and its validation
    • Validating Touchstone Models
    • Correlating simulation models versus measurements
    • Accurately modeling PVT in system simulations
    • Guidelines for achieving consistent results with different simulation tools
  • On-chip power and mixed-signal modeling methodology
    • Analog/mixed signal and power design methods
    • Approaches for system-level modeling of I/O buffers and voltage regulators
    • Digital Power Controllers modeling and correlation   
    • Chip-level modeling of power simulations for PDN Strategies
    • Mixed-signal behavioral models for SerDes phase-locked loops
    • Behavioral modeling of clock jitter and phase noise

Integrating photonics or wireless technology into electrical designs presents unique design challenges at chip, board, and system level. This track deals with the issues associated with the design and integration of photonics and wireless ICs, 3D packaging involving optical and electrical interconnects for data communication, emerging wireless and mmWave applications such as 5G, antenna in package integration, and automotive sensor applications such as Lidar.

Sample topics

  • Technology:
    • Microwave photonics
    • Photonic ICs and interconnects
    • Optical transceivers, Lidar, and sensors
    • Wireless interconnect technologies
    • Wireless and optical network convergence
  • Design, Layout & Assembly
    • Photonics and electrical components for 100/400/800Gbps optical communications
    • Lidar system integration and packaging
  • Modeling & Simulation
    • Silicon Photonics passive components such as optical waveguides, transitions, mode converters, phase rotators.
    • Silicon Photonics phase shifters, attenuators, MZM, ring modulators, coherent transmitters, and receivers
    • Electrical ICs such as laser driver, TIA simulation
    • Lasers and photo detectors
    • mmWave antenna array modeling and simulation
    • mmWave planar PCB circuits layout, modeling, and simulation
  • Compliance & measurements
    • Measurement and testing of optical/electrical ICs, transceivers, sensors
    • FCC qualification; interference mitigation Integrated optical links, optical interconnects
    • Measurement and testing of RF/mmWave ICs
    • Over the Air Testing (OTA) of Antenna in package (AIP) devices
    • Quality and reliability testing over temperature and voltage

Printed circuit board (PCB) materials and fabrication processes and the effects on the electrical properties and performance of the PCB’s modules and packages. This track considers those needs and analyzes the various solution options.

Sample topics

  • PCB, module, and package processing techniques
    • Fine registration improvements
    • Advanced stub mitigation including backdrilling
    • High aspect-ration vias
    • MSAP-modified semi-additive processing
    • Novel manufacturing techniques
    • Copper profile advances
  • Advanced laminate and electrical characterization
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Impact on materials for humidity, temperature, chemistries, special environments
    • Materials characterization and modeling
    • Thermal characterization and modeling
    • Advances in low loss laminates
    • Advances in copper surfaces including resin to copper adhesion techniques
    • Advances in thin dielectrics
    • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • PCB, module, and package design
    • Microvias, RF vias and thermal vias
    • Embedded optical channels
    • Embedded devices (active and passive)
    • Decoupling with Embedded Capacitor layers
    • Routing Techniques
    • Sockets and connectors
    • Hybrid board construction for performance and economy
  • 3D printing and additive manufacturing
  • Rigid-flex and multilayer flex circuit materials, design, and manufacturing
  • PCB and hybrid media advances for increased power delivery and thermal management
  • How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths
  • Other materials such as magnetic dielectrics and thermal management
  • Automotive and sensor materials advances

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, machine learning, virtual/augmented reality, and high-performance computing (HPC) present great challenges in I/O interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various I/O interfaces.

Sample topics

  • Memory interface
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
    • NV memory
    • Emerging memory interface (optical memory)
  • 2.5D/3D/SiP interface
    • HBM, HMC and Wide I/O interfaces
    • Proprietary or emerging 2.5D/3D/SiP I/O interfaces
  • High-speed parallel interface
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
    • Circuit architecture and techniques for improving signal bandwidth
    • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
    • Low-power designs
  • Signal/power integrity simulation
    • Supply noise induced clock and data jitter analysis
    • Channel crosstalk, simultaneous switching noise, and statistical timing models

Design-oriented modeling simulation and analysis are required for cost-effective power and signal integrity (SI) performance optimization of chip, package, board, and chip+package+board combinations. This track covers the broad range of topics required to best address those needs for modern microprocessor and digital systems.

Sample topics

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • System issues affecting PCB/package/chip/device power modeling
  • Interaction of protection devices
  • Application specific end-to-end system modeling
  • New technology design, including IoT design and 5G system co-design
  • First- and second-level interconnect analysis as it affects system performance
  • Sub-system interaction
  • System-level power and signal integrity
  • System co-design for high-speed signaling
  • I/O interoperability
  • Mixed-signal system design
  • System-level challenges of multi-voltage design
  • System-level modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP), module design
  • 3D/2.5D on-chip interconnect design and analysis, heterogeneous die
  • Performance trade-offs: electrical, mechanical, thermal

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

Sample topics

  • Design, architecture and/or SI analysis of complete backplane and cable interconnect systems
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification (validation) and correlation
  • PCI Express, Ethernet, and other standard-based architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Physical modeling and simulation
  • SerDes design techniques
  • System interconnect and switch fabric architecture
  • PAM-N vs NRZ vs other advanced modulation schemes system trade-offs/case studies
  • Serial link system performance evaluation techniques (e.g. COM, Salz SNR)
  • End-to-end link design, ideas, and algorithms that optimize link performance and latency while meeting reach and power requirements

Suggested panel topic: PCI-Express Gen 5 and 6 design ideas and challenges (they have the same baud rate)

Jitter, noise, crosstalk, ISI, and reflection cause errors. Track 8 covers techniques for measuring, analyzing, and minimizing these, as well as BER/SER/FER (bit/symbol/frame error ratio). Also covered are simulation and modeling of signal impairments and techniques that optimize performance.

Sample topics

  • Error ratio, SNDR (signal-to-noise-distortion ratio), level-mismatch/non-linearity and distortion analysis, measurement, and simulation
  • Measurement and estimation for:
    • Closed eye analysis via CTLE/FFE/DFE/CDR, and COM
    • Jitter and noise simulation, analysis, and measurement
    • Stochastic and deterministic, correlated and uncorrelated jitter, noise, crosstalk, reflection, and ISI (inter-symbol interference) modeling techniques
  • PAM4 signal measurement, analysis, and BER/SER/FER minimization
  • Machine learning (ML) and AI techniques for minimizing noise, jitter, and BER
  • Relationship between S-parameters and time domain errors, e.g. ERL (effective return loss)
  • Jitter and noise test and measurement for diagnostics and standards compliance
  • Time/frequency domain, phase noise, and white and colored jitter/noise spectrum analysis and prediction
  • Stressed eye testing: Jitter and interference calibration, tolerance measurement
  • Embedded/forward clocking and related jitter mitigation techniques
  • BER/SER/FER analysis, modeling, and optimization in the presence of FEC (forward error correlation) for Gaussian and burst errors
  • Channel/test fixture de-embedding and modeling

High-speed communication systems require increasingly complex signal-processing techniques; including equalization, modulation, synchronization, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Sample topics

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithms, modeling, and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction), error propagation, frame error rate (FER) analysis, modeling and implementation
  • FEC encoder and decoder algorithms, hard/soft detection and decoding
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Verification by measurement
  • Advanced modulation (PAM-n, QAM/coherent, Trellis Coded Modulation (TCM), etc.)
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling, and DC balance modeling
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
  • Back-channel training methods and performance
  • Carrier synchronization for coherent systems

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling, and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance, supply noise, and/or power induced jitter, and their impact on overall system performance.

Sample topics

  • System level PDN design strategy
    • Chip/package/board analysis and decoupling optimization
    • PDN performance versus cost, size, yield, reliability, etc.
    • System and PCB PDN modeling and simulation
    • PDN specifications, measurements, and correlation
    • System power noise and transients modeling and mitigation
    • Supply noise induced jitter analysis and optimization
  • Chip-level power distribution and regulation impact on system PDN performance
    • On-chip power grid inductance, resistance, and on-die decoupling
    • Dynamic and static voltage variations
    • On-chip regulator and power gating impact on power integrity
  • Power supply design
    • DC-DC converter and VRM design including GaN technology
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management for portable & mobile electronics
    • Digital control loops
    • Low-voltage, high-power designs
    • VRM and DC-DC converter modeling and simulation
    • AC-DC converters and its EMC and SI/PI impact on on-board, modules, and Data Centers
    • PMIC and its impact on PDN noise and power induced jitter
    • PDN optimization with PMIC

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

Sample topics

  • Design techniques to reduce or eliminate sources of EMI
  • Near-field and far-field radiation computations and scan
  • Pre-qualification testing for emissions
  • EMI radiation and suppression
  • EMI system susceptibility
  • Near-field coupling and crosstalk
  • Emissions and interference modeling
  • RFI/De-sense for mobile electronic devices
  • Noise characterization and containment
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Shielding at PCB, package, and system level
  • EMI measurements and measurement techniques
  • New shielding techniques and novel shielding materials
  • Meeting compliance requirements
  • Power supply consideration for EMI/RFI
  • EMI for high-density multi-port systems
  • ESD modeling

Advancements in measurement techniques are constantly being made for all aspects of signal and power integrity. This track focuses on the new techniques with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Sample topics

Measurement Methods for SI, PI, and EMI/EMC

  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
  • Signal integrity of fixture design for PCB, connectors, package, on-die, measurements
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Power supply noise measurement methods for dynamic load response, ripple injection
  • Passive device-measurement methods for on-die, package, connector, board testing
  • ATE and sub-systems design validation and production at speed testing

Standards for Measurements

  • Measurement methods for compliance with PAM4, Ethernet, PCIe, USB, DDR, etc.
  • IEEE and IPC standards for fixture removal and material properties measurements

Classic Measurements with Modern Instruments

  • 4-port differential pair measurement teardown
  • Capturing a PRBS data pattern with picosecond UIs

Hardware Technology and Architecture

  • Evolution of Network Analyzers, Oscilloscopes, Spectrum Analyzers
  • Next generation power delivery analyzers
  • One box does it all vs. traditional instruments vs. custom application

Calibration Algorithms and Quality of Data

  • Mixed standard calibration methods for non-coaxial reference planes
  • Fixture de-embedding techniques including EM-solver and measure-based models
  • Uncertainty of calibration methods
  • S-Parameter quality, causality, and passivity of measured data
  • Data mining techniques for multiport S-parameters including crosstalk

Simulation to Measurement Workflow

  • Reference Planes, Partial S-Parameters, Behavioral Models, As-Fabricated, etc.
  • Artificial Intelligence for improved simulation to measurement correlation

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers electromagnetic and microwave signal integrity analysis techniques as well as validation with measurements.

Sample topics

  • Signal integrity analysis with RF/Microwave techniques
  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • Techniques for interconnect de-embedding
  • Passive equalization and filtering
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
  • Electromagnetic modeling of channels including PCB traces, vias, packages, cables, and connectors
  • Simulation modeling and analysis of interaction between power distribution networks and signal interconnects
  • Via and via array design and optimization including BGAs, pin fields
  • Terahertz interconnects

Machine-learning algorithms can efficiently derive models for electronics and system design automation and enable fast, accurate design and verification of microelectronic circuits and systems. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

Sample topics

  • Static and dynamic neural network models for high speed channels and SerDes
  • Channel and SerDes performance optimization using PCA or CCA
  • ML and DoE techniques for optimizing designs with numerous parameter options
  • Generative and Bayesian surrogate models for response surface approximation
  • Machine learning for proactive hardware failure predictions
  • Supervised and un-supervised deep learning for hardware system performance tuning
  • ML techniques for improved rational function model extraction from S-parameters
  • GPU/TPU accelerated SerDes and channel simulation
  • Automated high-speed PCB layout design using deep learning
  • ML model portability & reusability across tools and tool flows
  • Training and inference tradeoffs for speed and accuracy

Session Formats

Boot Camps

Get up to speed — fast — with all-day boot camps covering core industry concepts, including signal integrity, power integrity, and more.

Tutorials

DesignCon’s three-hour tutorial sessions offer rich learning opportunities by allowing the speakers to cover timely topics in depth.

Technical Panels

These 75-minute panel discussions will host three or more visionaries as they present their insights and discuss opinions on a carefully curated topic.

Technical Papers

Presented in 45-minute sessions, the technical papers and their presentations provide new research, case studies and applications from thought leaders in the community.

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Conference Hours

Tuesday, January 26, 2021
9 a.m.–6 p.m.

Wednesday, January 27, 2021
8 a.m.–5 p.m.

Thursday, January 28, 2021
8 a.m.–5 p.m.