January 26–28, 2021

Santa Clara Convention Center, Santa Clara, CA

Meet the Technical Program Committee

The DesignCon 2020 Technical Program Committee (TPC) is composed of 97 leading experts in all levels of electronic design — chip, board, package, and system. These accomplished engineers and executives from top companies such as Cisco, Intel, Tektronix, Google, Apple, and Samtec rigorously review all call-for-paper submissions to develop a conference of the highest quality and industry relevance. The TPC's dedication and expertise helps make DesignCon the nation's premier conference for chip, board, and systems design engineers.

2020 Technical Program Committee (TPC)

Brice Achkir*, Distinguished Eng./Sr. Eng. Director, Cisco Systems
Joseph Aday*, Sr. Member of Technical Staff, Lockheed Martin
Maria Agoston*, Principal Engineer, Tektronix
Ravinder Ajmani*, Technologist, Electronic Design Engineering, Western Digital
John Andresakis, Technical Marketing Leader, Dow DuPont
Yianni Antoniades, Senior Electrical Engineer, Winchester Interconnect
Pervez Aziz*, Senior Principal Engineer, Nvidia
Seungyong (Brian) Baek, SI Architect, Apple
Rula Bakleh, SI/PI Consultant, Graphcore
Heidi Barnes*, SI/PI Applications Engineer, Keysight Technologies
Dale Becker, Distinguished Engineer, IBM
Wendem Beyene*, Principal Engineer, Intel
Luis Boluna, Sr. Application Engineer, Keysight Technologies
David Brunker, Technical Fellow, Molex
Robert Carter*, Vice President of Technology and Business Development, Oak-Mitsui Technologies
Chris Cheng*, Distinguished Technologist, HP Enterprise
Sam Chitwood, Product Engineer, Cadence
David Choe, Principal Applications Engineer, Cadence
Daehyun Chung, Sr. Manager, Hardware Engineering, Nvidia
Antonio Ciccomancini Scogna, Signal Integrity and EMC Technologist, Western Digital
Tom Cohen, Principal Engineer, Amphenol
Davi Correia, Signal Integrity Engineer, Carlisle Interconnect Technologies
O.J. Danzy, Senior Application Engineer, Keysight Technologies
Jan De Geest, Senior Staff SI R&D Signal Integrity Engineer, Amphenol
Jay Diepenbrock, Consultant, SIRF Consultants
Vladimir Dmitriev-Zdorov, Principal Engineer, Mentor Graphics, a Siemens Business
Greg Edlund, Senior Engineer, IBM
Jason Ellison*, Sr. Staff Signal Integrity Engineer, Amphenol
Paul Franzon, Cirrus Logic Distinguished Professor, Director of Graduate Programs, NCSU
Sanjeev Gupta*, R&D Manager, Intel
Sunil Gupta*, SIPI Technical Lead, Qualcomm Technologies
Robert Haller*, Sr. Principal Hardware Engineer, Extreme Networks
Gert Havermann, Signal Integrity Engineer, HARTING
Allen F. Horn III*, Research Fellow, Rogers
Rockwell Hsu, Technical Leader, Cisco Systems
Seunghyun Hwang, Sr. SI Engineer, Nvidia
Namhoon Kim, Chip Package Design Architect, Google
Beomtaek Lee, Sr. Principal Engineer, Intel 
Mike Li*, Fellow, Intel
Zhe Li, Hardware Engineer, Google
Cathy Liu*, Distinguished Engineer, Broadcom
Chris Loberg*, Marketing Manager, Tektronix
Om Mandhana, Staff Services AE, Cadence Design Systems
Henri Maramis, President / CEO, TrackingTheWorld 
Marko Marin*, Technical Account Manager, ANSYS
Jon Martens, Fellow, Anritsu
Mike (Mehdi) Mechaik*, Sr. Principal Application Engineer, Cadence Design Systems
Ted Mido, Principal R&D Engineer, Synopsys
Martin Miller, Chief Scientist, Teledyne LeCroy
Jose Moreira*, Senior Staff Engineer, Advantest
Zhen Mu*, Product Engineering Architect, Cadence Design Systems
Jim Nadolny, Engineering Manager, Samtec
Alfred P. Neves*, Chief Technologist, Wild River Technology
George Noh, Director of Sales and Marketing, Holt Integrated Circuits
Istvan Novak, Principal Signal and Power Integrity Engineer, Samtec
Dan Oh, Vice President, Samsung
Vishram Pandit*, Technology Lead (Signal/Power Integrity), Intel
Jongbae Park, Principal Engineer, Apple
Pete Pupalaikis, VP, Technology Development, Teledyne LeCroy
Kelvin Qiu, Signal Integrity Manager, Cisco
Fangyi Rao, Master Engineer, Keysight
Lee Ritchey, President, Speeding Edge
Gerardo Romo-Luevano*, Sr. Staff Engineer/Manager, Qualcomm
Steve Sandler, Managing Director, Picotest
Venkat Satagopan*, Sr. Staff Signal Integrity Engineer, Nvidia
Chris Scholz, Product Manager, Rohde & Schwarz
Christian Schuster, Professor, TUHH
Stefaan Sercu, SI R&D Engineer, Samtec
Yan Fen Shen, Analog Engineer, Intel
Masashi Shimanouchi, Design Engineer, Intel
Yuriy Shlepnev, President, Simberian
Bert Simonovich, President, Lamsim Enterprises
Chad Smutzer, Senior Engineer, Mayo Clinic
Mike Steinberger, Lead Architect, Serial Channel Products, SiSoft
Ransom Stephens*, Signal Integrity Sage, Ransom's Notes
Suresh Subramaniam, Distinguished Engineer, Apex Semiconductors
Madhavan Swaminathan, John Pippin Chair Professor in Microsystems Packaging & Emag, Georgia Tech
Donald Telian,  Owner/Consultant, SiGuys
Lars Thon*, Consultant, LT Engineering
Thomas To*, Director, Xilinx
Peter Tomaszewski, Sr Field Applications Engineer, Tektronix
Ambrish Varma*, Sr. Principal Software Engineer, Cadence Design Systems
Harald von Sosen, Principal Engineer, Mentor, A Siemens Business
Michael Vrazel, Systems and DV Manager, Texas Instruments
Min Wang, Technical Lead Manager, Waymo
Scott Wedge, Principal Engineer, Synopsys
Todd Westerhoff*, Product Marketing Manager, Mentor, a Siemens business
Markus Witte, Systems Engineer, Grimme
Randy Wolff, Signal Integrity Engineer, Micron Technology
Hsinho Wu*, Design Engineer, Intel
Ken Wu, Hardware Engineering Manager, Google
Chris Wyland*, Sr. Staff Engineer, Juniper Networks
Kai Xiao, Principal Engineer, Intel
Mobashar Yazdani*, Strategic Semiconductor Manager, Google
Iliya Zamek*, Architect, Technical Manager, HCL America
Geoffrey Zhang, Distinguished Engineer and Supervisor, Xilinx
Pavel Zivny, Domain Expert, Tektronix

*2020 track co-chair