Technical Panels

Hot topics debated by industry experts!

Monday, January 30, 2012

The Case of the Closing Eye -- De-Mystifying the Measurement Complexity - An Industry Panel
Panelists: Chris Loberg (Tektronix - Danaher), Ransom Stephens (Teraspeed Consulting, LLC), Mike Peng Li (Altera), Martin Miller (LeCroy Corporation), Greg Le Cheminant (Agilent Technologies), Eric Kvamme (LSI Corp.) and Tom Waschura (Tektronix)
Date/Time: Monday, January 30, 4:45pm - 6:00pm
Track: High-Speed Timing, Jitter and Noise Analysis
Click here for PDF of session slides.

Modern communication systems employ complex receivers that open the "closed EYE". Closed Eyes are difficult to specify so standards bodies have incorporated reference equalizers to measure the receiver stress in terms of an open EYE. These reference receivers and test patterns have conflicting requirements. Easy to mathematically model and implement in statistical eye simulations and scope software and represent the actual silicon hardware built by silicon providers. This panel explores why differences must exist between the reference EQ and efficient silicon implementation.

What is New in DC-DC Converters?
Panelists:V. Joseph Thottuvelil (GE Energy), Steven Weir (IPBLOX, LLC) and Chris Young (Intersil)
Date/Time: Monday, January 30, 4:45pm - 6:00pm
Track: Power Integrity and Power Distribution Network Design

The panelists plan to cover and discuss topics including but not necessarily limited to: trends, current state of the art in power density, selection criteria among packaging options (open frame, embedded, modules, semi-modules), state of the art and forecast of efficiency, power density, switching frequency, loop bandwidth, output noise, the signature and bandwidth of output periodic and random noise, set-point accuracy, trends of number of phases, new features of digital telemetry, interaction of DC-DC converter performance with the power distribution environment, and last but not least, new options and features of design tools for users.

Tuesday, January 31, 2012

Is It Time for an Analog Comeback?
Panelists: Brian Bailey (Brian Bailey Consulting), Jeff Miller (Tanner EDA), Mladen Nizic (Cadence Design) and Warren Savage (IPextreme)

Date/Time: Tuesday, January 31, 3:45pm - 5:00pm
Track: Analog and Mixed-Signal Design and Verification

It seems as if analog was almost a thing of the past. Designs converted analog signals into digital as quickly as they could, leaving only small amounts of analog off-chip. But today that analog circuitry has come on-chip. Radio's and high-speed communications are now fully integrated, power saving schemes are adding new types of analog content, signal integrity and high-speed issues often require analog analysis, and these are demanding better tools and flows to handle the mixed-signal aspects of a design. In addition, there are some parts of a design that operate at speeds greater than digital is capable of. With better tools, will the percentage of the chip consumed by analog increase again? Will the shrinking geometries cause even greater difficulties for analog?

Why Do We Need 3D Design Standards?
Panelists: Riko Radojcic (Qualcomm), Sumit DasGupta (Si2), Liam Madden (Xilinx), Raj Jammy (SEMATECH), Bryon Moyer (Techfocus Media) and Jim Hogan (Telos Venture Partners)
Date/Time: Tuesday, January 31, 3:45pm - 5:00pm
Track: System Co-Design: Chip/Package/Board
Click here for PDF of session slides.

This panel will explore whether the design community needs 3D IC standards to accelerate the adoption of 3D design, and if so, how the standards can be implemented, the priority of these required standards, what are the challenges in doing so and how to get started. It will also provide insights on how the many different industry groups are working together to prevent overlapping efforts or missing critical areas. In a typical 3D IC, functional tiers will likely be coming from different companies and at different process nodes, and also different foundries as well. Without effective standards, it is difficult to efficiently integrate different tiers into a common package using best-in-class tools from multiple vendors and test the result. It is not possible to ensure a single EDA vendor flow spanning across the design of tiers designed by different companies.

The Future of Measurements in High-Speed Serial Links
Panelists: Martin Rowe (UBM Electronics), Daniel Chow (Altera),  Bryan Capser (Intel),  Sam Stephens (AMD), Reginald Conley (PLX Technology) and Andy Baldman (University of New Hampshire InterOperability Laboratory)
Date/Time: Tuesday, January 31, 3:45pm - 5:00pm
Track: Test and Measurement Methodology

As high speed data rates keep increasing, traditional instruments like BERTs and real-time oscilloscopes are getting prohibitively expensive (>$300k for 25Gb/s requirements). Equipment from different industries and platforms. Oscilloscopes and BERTS can measure jitter. Today BERTs can produce waveforms and oscilloscopes and measure BER. The roles of test equipment are changing because today's high-speed digital signals act like microwaves. Thus, characterization of high speed clocks now requires spectrum analyzers, which traditionally have been used for RF measurements. Similarly, engineer now use VNAs, which as RF instruments, to test PCB designs. Furthermore, engineers are seeing new platforms, such as spectrum analyzers designed for real-time measurements and oscilloscopes that include spectrum analyzers. To make these measurements, engineers combine their expertise in high speed sampling with spectrum analyzer applications. This panel discussion will feature engineers who characterize components that run at today's highest speeds. They will share their experiences at making measurements and how they combine instruments because using a single instruments won't provide enough information about a signal or system. Attendees will learn how engineers use modern RF test equipment in conjunction with oscilloscopes and BERTS to get a more complete picture of a signal's jitter, amplitude, and bit-error rates.

Wednesday, February 1, 2012

Delivering on Time-to-Answer: Meeting Designers Needs in Test & Measurement
Moderator: Patrick Mannion, Editor in Chief, Test & Measurement World and EDN
Panelists: Dave Graef, Vice President and Chief Technology Officer, LeCroy Corporation; Kevin Ilcisin, CTO, Tektronix; Greg Peters, GM and VP of Component Test Division, Agilent; and Eric Starkloff, vice president of systems platforms at National Instruments
Date/Time: Wednesday, February 1, 3:45pm - 5:00pm

Designers face ever-shorter time-to-market windows and consistently look to their test equipment for faster 'time to answer'. Yet this requirement clearly flies in the face of the increasing complexity as designers deal with higher integration, multiple RF interfaces, multiple high-speed serial or parallel signaling protocols, multiple processors and a matrix of IC, board, software and system-level interactions and dependencies so fractal in nature that they frustrate even the most experienced test engineers and system designers.

Instead of looking at their design as though through a sieve, designers need clarity and instant system visibility. This panel pulls together the best minds in the industry to explore how this can be achieved. Join us as we discuss the nature of test, the interactions and issues designers face, how test technology is evolving to meet designers' needs and what lies ahead that you need to anticipate—now.