Sponsored Sessions

Take advantage of the variety of FREE SPONSORED TRAINING SESSIONS presented by industry heavyweights. Open to ALL attendees, the sponsored sessions give you in-depth hands-on solutions to specific design challenges. These aren’t product pitches or cleverly disguised marketing ploys; this is the “real stuff” that engineers want and need to get their jobs done.

The Chip-Package-System (CPS) Workshops, sponsored by Apache Design, are open forums for designers to exchange the latest ideas and information on current technologies for chip and package modeling, and system level verification for SI, PI, EMI and thermal. Two in-depth workshops will bring together key semiconductor companies and system houses from the electronics industry to share their expert perspectives and best practices on "CPS Methodology for Cost-Down and/or Reliability" and "CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications."

CPS Methodology for Cost-Down and/or Reliability
Date: Wednesday, February 1, 2012
Time: 10:15am - 12:15pm
Location: Ballroom H, Santa Clara Convention Center
Featuring Presentations By: Intel and Cisco

Meeting the performance and cost demands of today’s chip designs requires a comprehensive chip-package-system approach to analysis. A complete methodology should include accurately characterized models of all system aspects including chip, package and board, while providing simulation capabilities to enable engineers with enough knowledge and confidence to make optimal cost reduction, performance, and reliability decisions for their designs.

In this informative and educational workshop, representatives from the industry’s top semiconductor and system design companies will share their insights and expertise in the area of chip-package-system (CPS) convergence, and will discuss various aspects of analysis methodologies and technologies in terms of modeling, extraction and simulation. Topics will include comprehensive global power delivery optimization at the chip, package and board levels, system-level signal integrity analysis, along with case studies and real design examples.

CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications
Date: Wednesday, February 1, 2012
Time: 2:00pm - 4:00pm
Location: Ballroom H, Santa Clara Convention Center
Featuring Presentations By: Micron, LSI and Xilinx

3D stacked die and 2.5D Silicon Interposer chip designs with through-silicon vias (TSVs) have emerged as upcoming technologies, enabling designers to meet the performance, power, and form factor demands of today’s ICs. While it reduces the overall footprint of design real estate, 3D architecture also significantly improves vertical routing density and reduces wire length, thus allowing for improvements in communication time, robustness against signal integrity issues, and power consumption. However, 3D-IC designers face unique challenges such as thermal-induced EM and reliability issues, along with place and route congestion due to TSV insertion. To combat these challenges and achieve design closure requires 3D-ready modeling and simulation techniques.

This interactive workshop features experts from the industry’s leading semiconductor and system design companies who will examine the various modeling and simulation challenges in 3D-IC design. Methodologies for the analysis of power delivery network, chip-to-chip communication, and thermal integrity will be covered using real case studies on designs.