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SiSoft @ DesignCon

Visit SiSoft at DesignCon booth Number 100

SiSoft is proud to be a DesignCon 2013 Diamond Sponsor and a DesignTOUR Sponsor.

Exhibition Hours:
Tuesday, January 29, 2013 12:45 PM - 6:00 PM
Wednesday, January 30, 2013 12:30 PM - 6:00 PM

SiSoft

Visit Booth #100 and See How SiSoft Helps Customers Solve the World’s Toughest High-Speed Design Problems.

This year at DesignCon we’re talking about DDR4, 28Gb/s Serial Link Analysis and Correlating Simulations to Measurement. Stop by Booth #100 where we’ll be demonstrating DDR/4, 28 Gb/s and Statistical Discovery Analysis.

Have you started designing for DDR4 yet? Come see how Quantum-SI automatically processes simulation waveforms in accordance with this latest DDR standard. Are you designing serial links running at 28Gb/s? Learn how SiSoft is working with device vendors to certify and correlate IBIS-AMI models running at these speeds.

Conference Highlights:


Fast, Efficient and Accurate: Analytic Via Models that Correlate to 20 GHz

Tuesday, January 29
8:30 AM - 9:10 AM
Location: Ballroom F

Speakers
Dr. Michael Steinberger, Lead Architect of Serial Channel Products, SiSoft
Eric Brock, Principal Member of Technical Staff, SiSoft
Donald Telian, Principal SI Consultant, SI Guys

A comparison of modeled to measured results suggests that vias introduce dissipative loss beyond that predicted by modeling tools, especially at frequencies above 10 GHz. This session presents such a comparison based on measured results from several different test boards using different materials and layout approaches. It evaluates several hypotheses that might explain the additional loss, including leakage from radial TEM waves and interactions with ground vias. The conclusions are used to extend existing analytic via models and improve high-frequency behavior. The results of system correlations are presented, demonstrating signal path correlation up to 20 GHz.


Applying Microwave Techniques to Digital Systems: A Simple Case Study

Tuesday, January 29
11:05 AM - 11:45 AM
Location: Ballroom B

Speakers
Dr. Michael Steinberger, Lead Architect of Serial Channel Products, SiSoft
Paul Wildes, Principal Signal Integrity Engineer, SiSoft

Techniques well known in the field of RF/microwave analysis can be applied to good effect in high-speed digital design. Often the greatest obstacles are not technical, but arise from differences in methodology and terminology in the microwave area. This session seeks to help bridge that gap with a case study, demonstrating the application of a long-established microwave filter design (drawn from a classic RF text) to a very current problem in high-speed digital design: the conditioning of a processor's clock source to obtain high duty-cycle accuracy. The solution, a four-pole Chebyshev filter, is robust and compact. It is implemented in standard PCB technology, without any unusual spacing or handcrafting techniques, and with no discrete components. Measured data is presented from a proof-of-concept test board and from the final production board.


Measurement-Based Simulation: Increasing IBIS-AMI Model Accuracy with Data from Lab Measurements

Wednesday, January 30
10:15 AM - 10:55 AM
Location: Ballroom F

Speakers
Dr. Michael Steinberger, Lead Architect of Serial Channel Products, SiSoft
Paul Wildes, Principal Signal Integrity Engineer, SiSoft
Anders Ekholm, Expert, Signal Integrity and Timing Analysis, Ericsson AB
Nicke Svee, Hardware Designer, Ericsson AB

The combination of a spectrum analyzer and specific data patterns can be used to reliably identify different jitter and noise sources in SerDes transmitters and receivers, quantifying the associated impairments precisely. This paper uses data measured on a real system to explain the procedures for measuring clock-based DCD, data-based DCD, reference clock phase noise, clock leakage, power supply noise, transmission loss, and crosstalk in the serial channels at the system level. Once the different impairments are quantified, jitter and noise budgets are extracted that can be used by standard serial link simulation tools. This allows data extracted from silicon characterization to be used to accurately predict operating margins during new system design. This paper will demonstrate the derivation of device jitter and noise budgets along with the correlation of simulated results to the original measured data.

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