Mentor Graphics

Mentor is Platinum sponsor for DesignCon 2015, please visit us at Booth #935 and come to our workshop on the Second Floor in Room 201.


Mentor Graphics® is the worldwide market leader in PCB systems design and analysis technologies. Mentor Graphics will be showcasing its advanced HyperLynx and Nimbic technologies for electrical sign-off, including a complete analysis environment for DDRx designs, multi-gbps channel analysis, full-wave 3D electromagnetic modeling, and power distribution design. Visit booth #935 to learn more about Mentor’s technologies and best practices for virtual prototyping or by attending Mentor Graphics technical presentations.

Featured demonstrations:

  • Signal and power integrity analysis
  • IC/package/board co-optimization
  • Automatic stack-up design

Technical Workshop – Wednesday January 28th

8:30 am – 10 a.m.

A Holistic Approach to IC, Package and Board co-optimization

Level: Intermediate

Today’s leading edge IC packaging technologies require a holistic co-design methodology that streamlines the planning, assembly, and optimization of the chip(s), package, and PCB while assimilating the physical and logical interactions between each design domain. Package pin-outs and other packaging interconnect structures, such as bridges and interposers, must not only be optimized based on die level constraints, but also on the constraints, escape routing, and pin-outs of critical interfaces within the PCB. This session outlines a methodology for the concurrent design and optimization of chips, packages and PCBs

10:15 a.m – 11:45 a.m.

Designing Manufacturable Stackups – A Comprehensive Approach to Stackup and SI Modeling

Level: Basic knowledge of PCB construction, materials and single integrity, specifically for complex, flex and rigid-flex boards

As electronic products become more complex, comprising a range of high-speed, rigid and flex PCBs, it has become critical to accurately design and communicate stackups to avoid lengthy exchanges with fabricators, and ensure manufactured boards meet design intent.

Designing stackups with an awareness of available material characteristics and cost variations can help to reduce PCB costs, improve final product quality and shorten manufacturing lead-time.

In this session we will discuss the use of an industry-proven software solution to design the most challenging stackups, considering all mechanical and SI constraints. By modeling with standard industry materials or material libraries provided by PCB suppliers, designers and NPI engineers can model and verify thickness, impedance and losses quickly and accurately on the first attempt, for even the most complex multi-zone structures.

2:00 – 3:30 pm

DDR INTERFACE AND SERDES CHANNEL DESIGN FOR HIGH PERFORMANCE FPGA – based PCBs

Designing high performance printed circuit boards (PCB) is a complex and very demanding task for any design team to undertake. For example, PCB designs employing FPGA devices which support DDR4 memory interfaces operating up to 2667 Mtps and SerDes channels running at 28Gbs+ present design teams with unprecedented timing closure and signal integrity challenges. At higher speeds the DDR interface data valid windows are greatly reduced and achieving SerDes channel bit-error rates (BERs) with sufficient eye openings is extremely challenging. General PCB layout guidelines are useful but not sufficient to guarantee success and interpreting and enforcing such guidelines is commonly difficult to implement due to design specific factors such as budget, time, or engineering resource limitations.

In this session Altera and Mentor Graphics team up to identify key high speed PCB design challenges and solutions using a combination of Altera’s Quartus II design software, Altera’s Arria 10 IBIS-AMI models, and Mentor’s HyperLynx design and verification tools.  A novel approach to DDR timing interface design closure and serial link transceiver (Tx) tap setting optimization to achieve BER and eye opening requirements is introduced in detail.

3:45 – 5:00 pm

Electromagnetic Simulation for Electronic Systems

Packages and boards are playing an increasing role as a way to increase speed and density while reducing power and form factor of electronic systems. This is part of a trend called sometimes “more than Moore”, to refer to factors in addition to scaling ICs. This session focuses on the simulation of the package-board system, which is becoming increasingly more complex and often requires solving the electromagnetic fields. The Nimbic product suite will be highlighted, delivering Maxwell-accurate 3D full-wave broadband, quasi-static, and hybrid electromagnetic (EM) field solvers.

Technical Workshop – Thursday January 27th

2:00pm - 2:40pm

DDR4 Board Design and Signal Integrity Verification Challenges

From a PCB board design and validation perspective, DDR4 has some significant changes from the previous generations. The data signals will no longer be validated using tradition setup and hold measurements, and are no longer center terminated. Moreover, Simultaneously Switching Output (SSO) becomes a factor at DDR4 speeds, and is now supported by IBIS 5.0. These and other changes have implications to designing, validating and debugging a DDR4 system. This presentation will walk through these changes, and the factors that the PCB design engineer needs to keep in mind while designing a successful DDR4 system.

2:00 pm – 2:40 pm

Accurate statistical analysis of SERDES links considering correlated input patterns, data-dependent edge transitions, and transmit jitter

Statistical analysis is capable of reaching BER levels as low as1e-12 and beyond. Still, statistical simulation is unable to consider some important effects/impairments. Among those are: correlation of logical states in the input pattern, data-dependence of transition waveform shapes (the shape depends on a number of previous states) manifesting non-LTI behavior, and accurate consideration of transmit jitter. We propose a way to accurately consider all these effects in a single statistical analysis flow. The algorithm is represented by the structure that naturally accommodates different states and transitions between them, allowing correlated input, data dependent transitions and accurate modeling of transmit jitter.