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  • Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center 
    | Santa Clara, CA

Conference Overview

1 Pass. 14 Tracks.


DesignCon offers an in-depth, three-day conference program curated by our Technical Program Committee (TPC) — an expert panel of more than 90 industry professionals. With over 100 technical paper sessions, panels, and tutorials spanning 14 tracks, DesignCon's educational content covers all aspects of electronic design, including signal and power integrity; system co-design; and test and measurement methodologies. PLUS! New this year: Acquire an IEEE credit for every hour you spend at the conference. Learn more.

Conference Hours

Tuesday, January 30
9:00 a.m.–6:00 p.m.

Wednesday, January 31
8:00 a.m.–5:00 p.m.

Thursday, February 1
8:00 a.m.–5:00 p.m.

Conference Tracks


Select a track name for more details.

Die, interposer, and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, and packaging levels, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Achieving first-pass design success with today's complex systems requires ever improving simulation approaches. Chip-to-chip data channels, clocks, and power delivery solutions each have specialized modeling requirements that must be met to accurately predict and deliver expected system performance while accelerating design cycles. The use of IBIS-AMI models, for example, must be done with confidence that the model is adequate, awareness of potential model limitations, and full exploitation of the model's features and benefits. This track addresses challenges and solutions for design and verification that may involve various analog and algorithmic modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability.

Integrating photonics into electrical design to meet higher data rates presents unique technical and design challenges. Emerging modulation schemes coupled with high channel losses, nonlinear optics, use of complex equalization, re-timers, and integration of FEC within the receiver are just a few technical complexities. Integrating photonics brings other new challenges in terms of power, thermal, small footprint, high density, etc. — considerations the engineers need to solve to enable high-performance and high-data-rate designs.

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

High-speed data transfer up to 56 Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112 Gbps? Can PCB support high-current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization tools, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in IO interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, and form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various IO interfaces.

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

Jitter, noise, crosstalk, ISI, and reflection cause errors. This track covers techniques for measuring, analyzing, and minimizing BER (bit error ratio), SER (symbol error ratio), and FER (frame error ratio), including simulation and modeling of signal impairments and techniques that optimize performance.

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling, and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

Welcome Reception


Kick off the show with this exclusive networking event. Enjoy complimentary snacks and drinks on Tuesday, January 30, from 6:00 to 8:00 p.m. at the Santa Clara Ballroom at the Hyatt Santa Clara. Open to all-access, two-day, and boot camp pass holders, as well as media representatives, speakers, TPC members, and exhibitors. (Badge required for entry.)
Sponsored by: Keysight Technologies


Justification Toolkit

Need help securing the budget or time off to attend DesignCon? We've created several resources for you.           


Group Discounts

Save up to 25% when you register with a group of three or more! The more colleagues you bring, the more you save.