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Conference Tracks

Optimize Chip-Level Designs for Signal and Power Integrity

Chip-level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the on-chip level, from interconnect topologies, transceiver technology and design, to noise and jitter mitigation strategies.

 

Overcome Analog and Mixed-Signal Modeling and Simulation Challenges

As capabilities expand and complexity grows, today’s chips and systems require new modeling and simulation approaches that ensure design success, but give useful results in a reasonable amount of time. Faster I/Os and waveforms, as well as RF, MEMS, and sensor components require specialized models that take into account analog and high-frequency effects. Yet, mixing these with other models for simulation must be done efficiently to capture critical effects and still give quick answers. This track addresses challenges and solutions for design and verification that may involve various modeling abstractions and simulation approaches to predict critical aspects of system performance.

 

Wireless and Photonic Integration

The aim of this track is to provide a forum covering practices and methodologies used in emerging system designs and applications leveraging wireless and photonic technologies as media for data transmission. There are many challenges in system integration, especially for signal integrity and power integrity. This track looks at what happens when multiple data transmission technologies converge in one design.

 

System Co-Design: Chip/Package/Board: Modeling and Simulation

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

 

Characterize PCB Materials and Processing Characterization

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

 

Apply PCB Design Tools

High-speed data transfer and telecommunications are supported by PCB platforms that typically constitute more than 80% of the channel length while concurrently supporting power delivery, mixed-signal requirements and full-blown serial data speeds. This track explores effective high-speed design and design choices using a wide range of E-M modeling techniques, PCB characterization tools, and test platforms to optimize PCB platforms such as backplanes, mid-planes, and daughter cards combined with separable interconnects and optical channels.

 

Design Parallel and Memory Interfaces

Memory and parallel interface designs continue to be challenged with complex performance requirements including bandwidth, power consumptions, and form factors. This track addresses the latest design techniques and signal and power integrity issues to meet these performance requirements for various chip-to-chip interfaces. I/O system used in 2.5D, 3D, on-chip, SiP, and MCM are covered in this track in addition to conventional on-board interface designs.

 

Optimize High-Speed Serial Design

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

 

Detect and Mitigate Jitter, Crosstalk, and Noise

The only relevant signal integrity issue is whether or not a system operates at the required bit error ratio (BER). This track concentrates on the causes of errors, including, but not limited to jitter, crosstalk, and noise, and techniques for measuring and estimating BER performance such as total jitter, eye height, and BER contour.

 

Leverage High-Speed Signal Processing for Equalization and Coding

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and forward error-correction (FEC) methods. This track covers design, modeling, analysis, and implementation of such techniques.

 

Ensure Power Integrity in Power Distribution Networks

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of supply noise and its impact on overall system performance.

 

Achieve Electromagnetic Compatibility and Mitigate Interference

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

 

Apply Test and Measurement Methodology

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

 

Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

Analysis of signals on interconnects with high data rates often includes the extension of techniques originally developed for digital and RF/microwave systems. This track covers signal integrity analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.