Conference Tracks

Youngsoo Lee heads on-chip power integrity design methodology as one of technical leaders of the design technology team at Samsung LSI. She has considerable experience in the on-chip power integrity field, from IP to the full chip level. Since 2005, she has been playing a leading role in the development of Samsung's power integrity flow for 90- to 28-nm processes. Currently, she is working on a power integrity flow for advanced process nodes, such as 20 and 14 nm, and extending her research to package and off-chip power integrity solutions.

Dongyoun Yi received a bachelor's degree in computer engineering from Seoul National University in 2010 and joined Samsung Electronics as an assistant engineer, playing a significant role in chip power integrity-related design methodology. In particular, he has been developing a key component of Samsung's early-stage analysis methodology.

Mandy (Ying) Ji has been a system design engineer at Rambus Inc. since 2010. She is responsible for the physical design and signal and power integrity analysis of Si interposers, packagse, and boards. Previously, she worked at Sun Microsystems as a signal integrity engineer. She received her master of science degree in electrical engineering in 2007 and a PhD in mechanical engineering in 2004.

Ming Li has been a packaging engineer at Rambus Inc. since 2000. He is responsible for advanced IC packaging development, IC package design and substrate layout, and thermal and mechanical analysis of IC packages. Previously, he worked at Sandia National Lab as a research associate, at Tessera Inc. as a modeling engineer, and at PerkinElmer Inc as a senior packaging engineer. He holds bachelor's, master's, and doctoral degrees in materials science and engineering.

Julia Cline is currently manager of a system engineering team at Rambus Inc. Since joining Rambus in 2005, she has held positions as a product engineer and a digital circuit designer working on solutions for PS3 and HDTV customers. In her current role, she manages a team responsible for system solutions and package designs to validate Rambus technology. Cline received her master of science degree in electrical engineering and computer science from the Massachusetts Institute of Technology and her bachelor of science degree in electrical engineering from Brown University.

Dave Secker is a technical director in systems engineering at Rambus Inc., where his responsibilities include physical design, modeling, and optimization of high-speed signal interconnect and power delivery networks at the IC package and system board levels. Previously, he worked at Los Alamos National Laboratory as a research assistant. Secker received his master's degree in electrical and computer engineering from the University of Arizona in 1996.

Kevin Cai is a senior principal engineer at Rambus Inc. Earlier, he worked at Juniper Networks, Sun Microsystems, and Nortel Networks, specializing in high-speed signal integrity, system design and test, and material characterization. He holds a PhD degree in electrical engineering.

John Lau has been an ITRI fellow of the Industrial Technology Research Institute since January 2010. Earlier, he was a visiting professor at Hong Kong University Science and Technology; director of the Microsystems, Modules and Components Laboratory with the Institute of Microelectronics in Singapore; and a senior scientist/member of the technical staff at Hewlett-Packard/Agilent. With more than 30 years of R&D and manufacturing experience, he has authored or co-authored more than 300 peer-reviewed technical publications and more than 100 book chapters, and has given more than 250 presentations. He has authored or co-authored 16 textbooks on advanced packaging, lead-free soldering and manufacturing, solder joint reliability, and 3D MEMS packaging. Lau earned his PhD degree in theoretical and applied mechanics (University of Illinois) and three master of science degrees, in structural engineering, engineering physics, and management science.

Pei-Jer Tzeng has been with Electronic and Optoelectronic Research Laboratories at the Industrial Technology Research Institute (ITRI) in Hsinchu, Taiwan, since 2002, working in the areas of process integration and characterization of MOS devices, gate dielectrics, high-k materials, and their applications in DRAM and nonvolatile memory. Currently, he is working on process integration of exploratory 3D IC technology. He earned a PhD in engineering and system science from National Tsing Hua University, Hschinu, Taiwan., in 2002.

Chau-Jie Zhan is an engineer in the Assembly and Reliability Department of the Industrial Technology Research Institute in Taiwan. He areas of study have included flip-chip packages, lead-free assembly processes, 3D chip stacking, and electromigration in solder joints.

Ching-Kuan Lee received her Ph.D. Degree in Chemistry from Fu Jen Catholic University, Taiwan, R.O.C., in 2001. Since 2003, she has been with the Industrial Technology Research Institute (ITRI), Material and Chemical Research Laboratories, and shifted to Electronics and Optoelectronic Research Laboratories as a member of the Packaging Technology Division in June 2006, and is mainly responsible for microbumping process. The focus of her work is chemical metallization process and process development of advanced Package technology.

Thomas L. Anderson is vice president of marketing for Breker Verification Systems. His previous positions have included product management group director of advanced verification systems at Cadence, director of technical marketing in the Verification Group at Synopsys, vice president of applications engineering at 0-In Design Automation, and vice president of engineering at Virtual Chips. Anderson has presented more than 100 conference talks and published more than 150 papers and technical articles on such topics as advanced verification, formal analysis, SystemVerilog, and design reuse. He holds a master of science degree in electrical engineering and computer science from the Massachusetts Institute of Technology and a bachelor of science degree in computer systems engineering from the University of Massachusetts at Amherst.

Shashank Prasad is a senior R&D engineer at Cadence Design Systems Inc. He graduated in Computer Science from IIT Kanpur, India, and has 18 years of EDA software development experience in wide ranging fields such as schematic capture, spice simulation, and digital IC place and route tools. His recent research areas are in the field of hierarchical design methodology for multimillion-gate chips. He has several international publications in this area.

Kamal Preet Singh is a senior R&D engineer at Cadence Design Systems Inc. He graduated in electronics engineeringand has 12 years of EDA software development experience in such wide-ranging fields as digital design and implementation of state-of-the-art SoCs.

Joohee Kim (S'09) received her bachelor's and master's degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejeon, South Korea) in 2008 and 2010, respectively. She is currently pursuing a PhD degree in electrical engineering from KAIST. Her research interests include TSV modeling and failure analysis in TSV-based 3D ICs.

Daniel Hyunsuk Jung received a bachelor of science degree in electrical engineering from Case Western Reserve University in 2010. He is currently pursuing a master of science degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejeon, South Korea). His research interest is TSV failure modeling and analysis in 3D ICs.

Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and a Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. He is currently a Professor at the Electrical Engineering and Computer Science Department. Since joining KAIST, his research has centered on modeling, design, and measurement methodologies of hierarchical semiconductor systems including high-speed chip, package, interconnection, and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D semiconductor packages, system-in-package(System-in-package), and SoP(System-on-package). He was on a sabbatical leave at Silicon Image Inc., Sunnyvale CA, as a staff engineer during the 2001 to 2002 academic year. He was responsible for low noise package design of SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the director of the Satellite Research Laboratory of Hyundai Motors for EMI/EMC modeling of automotive RF, power electronic and cabling systems. He has more than 210 publications in refereed journals and conferences. Dr. Joungho Kim has been the chair or the co-chair of the EDAPS workshop since 2002. Currently, he is an Associated Editor of the IEEE Transactions of Electromagnetic Compatibility.

Bumhee Bae received his B.S and M.S degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing a Ph.D. degree in electrical engineering. His research interests includes EMI/EMC susceptibility of mixed-mode system with chip-package-PCB hierarchical structures.

Jonghyun Cho received B.S. and M.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2008 and 2010, respectively. He is now a Ph.D. candidate in electrical engineering from KAIST. His research interests include Si-interposer design, TSV noise coupling, and TSV depletion effects in TSV-based 3D IC.

Sunkyu Kong received a B.S. degree in electrical and electronic engineering from Chungnam National University, Daejeon, Korea. He received a M.S. degree from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing a Ph.D. degree in electrical engineering. His research interests includes EMI/EMC issues in analog-digital mixed-mode system with chip-package hierarchical structures.

Jonghoon J. Kim received B.S in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he is currently pursuing the M.S. degree in electrical engineering. His research interest includes current probing and wafer testing structures using inductive coupling in multi-layer PCBs, as well as on chip level.

Yujeong Shim is a senior signal integrity engineer at Altera Corporation. Her responsibility includes jitter modeling on high speed serial links and power distribution network design on system level. She received the B.S, the M.S and the Ph.D degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2005, 2007, and 2011 respectively. She worked as a visiting researcher at Silicon Image, Inc., Sunnyvale, California, US in 2008. In 2009, she was involved as an internship in RF and mm-wave modeling and characterization team at IMEC, Leuven, Belgium. She is an author/a co-author of 32 IEEE SCI journal /conference, and received the best paper awards at the 2007 Electromagnetic Compatibility (EMC) Compo, Torino, Italy and the DesignCon 2011 event.

Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and a Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. He is currently a Professor at the Electrical Engineering and Computer Science Department. Since joining KAIST, his research has centered on modeling, design, and measurement methodologies of hierarchical semiconductor systems including high-speed chip, package, interconnection, and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D semiconductor packages, system-in-package(System-in-package), and SoP(System-on-package). He was on a sabbatical leave at Silicon Image Inc., Sunnyvale CA, as a staff engineer during the 2001 to 2002 academic year. He was responsible for low noise package design of SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the director of the Satellite Research Laboratory of Hyundai Motors for EMI/EMC modeling of automotive RF, power electronic and cabling systems. He has more than 210 publications in refereed journals and conferences. Dr. Joungho Kim has been the chair or the co-chair of the EDAPS workshop since 2002. Currently, he is an Associated Editor of the IEEE Transactions of Electromagnetic Compatibility.

Ravi Surepeddi is working as a technical lead at Advanced Micro Devices Inc. Earlier, he was a Technical Action Group member to IEEE VHDL-VITAL through Texas Instruments. Surepeddi has nearly 50 publications for various journals and conferences in the areas of formal verification, structured OVM/UVM verification, computer architecture, image processing, pattern recognition, wireless systems design, and EDA.

Jason has spent most of his high-tech career in EDA industry, after starting as RD developer at Intel for random logic layout tool he moved on to Philips Semiconductors being part of multi-media design team; He later joined Avant! by leading the specialist team of Apollo product line before switching the interest into transistor level arena by joining Nassda as product specialist; Jason has been in Synopsys AMS organization since 2005 and dedicated in leveraging Synopsys CustomSim simulation technology with extended ERC/ESD solution.

Takao Inoue, senior RF platform engineer at National Instruments, received his PhD from the University of Texas at Austin and his MSEE and BSEE degrees from Oregon State University.

Andrew Becker currently works for Cray Inc. as a senior signal integrity engineer where he has been employed since 2004. Previously he has worked on 40Gbps long-haul transceivers for StrataLight Communications (now Opnext) in the SF Bay area, and for Lucent Technologies, Bell Laboratories in Murray Hill, NJ. He has a Master's Degree in Electrical Engineering from Stevens Institute of Technology in Hoboken, NJ and a BS in Physics from Binghamton University, State University of New York.

Michael Higgins is a Principle Engineer at Cray Inc. He has over 20 years of experience designing, analyzing, and validating custom processors, memory subsystems, and high-speed communication channels for supercomputers while working for Cray Research, Inc., Silicon Graphics, Inc., and Cray Inc. Mike holds a B.S.E.E. from the University of Minnesota.

Michael Steinberger, lead architect at SiSoft Inc., has more than 30 years' experience in the design and analysis of very high-speed electronic circuits. He is currently responsible for the architecture of SiSoft's Quantum Channel Designer tool for high-speed serial channel analysis. He started his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high-speed digital backplanes used throughout Lucent's transmission product line. Before joining SiSoft, Steinberger led a group at Cray Inc., performing SerDes design, high-speed channel analysis, PCB design, and custom RAM design. He holds a PhD from the University of Southern California and has been awarded 14 patents.

Paul Wildes is a consulting engineer with SiSoft Inc. where his work focuses on signal integrity in high-end communications and networking platforms. He spent more than twenty years designing circuits and channels at Cray Inc. Mr. Wildes received the BS and MS degrees in Electrical Engineering from the University of Wisconsin, and has been awarded 2 U.S. patents. Previously he developed semi-custom IC chips at Bell Labs, and did Unix kernel development at Astronautics Corporation in Madison, Wisconsin.

Bing Chuang is a Senior Member of Technical Staff II at Rambus Inc., where he has been for the past 6 years. His responsibilities include design-for-test, behavioral model validation and mixed-signal simulation of high speed designs. His current interests include DFT methodologies for mixed-signal, 3D-SIC and low power designs. He received the B.S. degree in Computer Engineering with Comprehensive Honors from the University of California, Santa Cruz in 2004, and the M.S. degree in Computer Science and Engineering with Distinction from the Santa Clara University in 2006.

Sumit Vishwakarma joined Synopsys Inc. in 2004 as an application consultant for Synopsys RF tools and later saw his role extended to support of full analog/mixed-signal products. He graduated from Arizona State University, where he worked on an Intel Corp. research project on ultra-wideband technology. Upon graduation, he published an IEEE paper on UWB front-end design. He currently has five SNUG publications in the field of AMS.

Kaneez Tumpa received a B.S. degree in Electrical Engineering from Bangladesh University of Engineering and Technology in 2002, and an M.S. degree in Electrical Engineering from San Jose State University in 2005. In 2005, she joined the technical staff at Rambus, where she is part of central design-for-test group and provides manufacturing test support of high-speed mixed-signal designs.

Aldo Morales has a PhD in electrical and computer engineering from the State University of New York at Buffalo. He has been involved in teaching signal processing, microprocessors, software applications, and local area networks for many years. Morales received an Engineering Society Outstanding Teaching award from the Pennsylvania State University College of Engineering and an Educator of the Year award from Penn State DuBois; was funded through the College of Engineering and IEEE Mountain Section (PA) to develop a modern LAN; and was instrumental in developing an advanced computer laboratory for the EET and IST programs at Penn State DuBois with grants from the Shared University Research Grant, IBM. Morales is the PI for a three-year Ben Franklin Technology Partners Grant that established the Center of Excellence in Signal Integrity at Penn State Harrisburg and has won a number of best-paper awards.

Sedig S. Agili has a PhD in electrical and computer engineering from Marquette University. In addition to a wealth of teaching experience, including courses and laboratories in electronic communications, network analysis, fiber optics, electronics, and electromagnetic fields, Agili has industrial experience, having designed optical projection and heads-up display systems. From 2001 to present, he has been involved in supporting and consulting local connector companies in signal integrity. He was the PI for the grant from the Pennsylvania State University, "High-speed Signal Integrity Research Related to Communications Link Components," and Co-PI for the three-year Ben Franklin Technology Partners Grant that established Penn State Harrisburg's Center of Excellence in Signal Integrity. He was a co-author for the Best Poster Paper award at the IEEE International Conference on Consumer Electronics 2007 for the paper "Transmitter Pre-emphasis and Adaptive Receiver Equalization for Duobinary Signaling in Backplane Channels."

Ashraf Umar is a graduate student in the Department of Electrical Engineering at the Pennsylvania State University, Harrisburg. He received his bachelor of engineering degree in electrical engineering from Ahmadu Bello University, Zaria, Nigeria.

Marcel Welpot worked at the Signal Integrity Lab at the Pennsylvania State Univeristy, Harrisburg, as an exchange student from Germany's Darmstadt University of Applied Sciences.

Mike Resso is a signal integrity application scientist in the Component Test Division of Agilent Technologies and has more than 25 years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high-speed digital interconnects using time-domain reflectometry and vector network analysis. He has authored more than 30 professional publications, including a book on signal integrity. Resso has been awarded one U.S. patent and has twice received the Agilent Spark of Insight Award for his contribution to the company. He received a bachelor of science degree in electrical and computer engineering from the University of California.

Ryan Mosley is a senior group manager for modular instruments at National Instruments.

Brian MacCleery is the principal product manager for clean energy technology at National Instruments. His mission is to facilitate the design, prototyping, and deployment of advanced embedded systems technologies to make clean energy less expensive and more abundant than fossil fuels. He received his bachelor's and master's degrees in electrical engineering from Virginia Polytechnic Institute and State University, where he completed his graduate research in electromechanical modeling and simulation and led multidisciplinary student teams in the development of novel magnetic levitation and propulsion designs for energy-efficient rapid transit.

Oleg Stepanov joined National Instruments Toronto in 2006 as a member of the Simulation and Modeling Group. His research interests are in the areas of analog circuit and electromechanical system simulation. He received his BASc degree in electrical engineering from the University of Toronto.

Muris Mujagic works at National Instruments Toronto as a member of the Simulation and Modeling Group. His primary responsibilities include enhancing and maintaining the Multisim SPICE simulation engine. He received his BASc degree in computer engineering from the University of Waterloo (Ontario) in 2005 and completed his MASc degree in electrical (biomedical) engineering at the University of Toronto in 2007.

Mahmoud Wahby joined National Instruments in 2011 and has focused on the application of SPICE circuit simulation in different industry applications in his role as a product marketing engineer. He received his BSc in electrical engineering from Ain Shams University, Cairo, Egypt, in 2008 and earned his MASc in electrical engineering from Queen's University, Kingston, Ontario, in 2011, working extensively on the simulation and modeling of microwave-frequency passive components, mainly antennas and filters.

Sanku Mukherjee is a Senior Member of Technical Staff II at Rambus Inc. His current interests include high speed system design, modeling and optimization of high-speed signal interconnect, post-silicon characterization and product analysis of modern high speed memory architectures. He has received his B.Tech degree in Electronics and Communication Engineering from Indian Institute of Technology, Guwahati and his Masters degree in Electrical Engineering from Michigan State University, USA in 2005. Prior to Rambus, he has worked in system design functions at NVidia Corp, USA and NetXen Inc, USA. He has several papers and publications in leading technical conferences and journals in the areas of signal integrity and system engineering design.

Narayanan Mayandi is a senior systems engineer at Rambus India Design Center. He is responsible for the system design, silicon characterization and validation of high speed serial IO and memory interfaces. He received his Bachelor Degree in Electronics & Communications Engineering with distinction from Anna University, India. Prior to Rambus, he was with Product Engineering Serivce group at L&T Infotech.

Sreeja Menon is a Senior Member of Technical Staff II at Rambus, India Design Center. She has more than 8 years of experience working on design and verification of digital controllers involving bus protocols such as PCIe, AMBA,OCP and memory protocols such as XDR1/XDR2. In her current role, she works on architecture definition of test chips for validating various high speed designs and on logic design of memory controllers. She has received her Bachelor’s degree in Applied Electronics and Instrumentation Engineering from University of Kerala, India.

Norman Chan is the Senior Principal Engineer at Rambus Inc. He is responsible for new Design Methodologies in Logic Design, Timing Analysis, test chip architecture and Low Power Design Flow. He has over 15 years in the area of logic and circuit design, process technology enabling and backend design, for various industrial standard and Rambus proprietary interfaces for products like entertainment consoles, HDTV and DLP projectors. His expertise and are if interests include high-speed mixed-signal design and enabling EDA tools/flows/methodologies for high performance and low power integrated circuit design. He graduated summa cum laude with a B.S. degree in electrical engineering from University of California, Los Angeles.

Arul Sendhil is currently a Manager at Rambus India Design Center. He leads the hardware engineering team, responsible for the system design, silicon characterization and validation of high speed serial I/O and memory interfaces. He received his Bachelor Degree in Electrical & Electronics Engineering with Honors from M.K. University, India and an MBA degree from M.K. University, India. Prior to Rambus, he was with the Mixed Signal Test & Product engineering group at Alliance Semiconductor.

Greg Caswell is widely recognized as a pioneer in surface-mount technology and has 40 years of experience in the electronics industry. Currently, he is a senior member of the tecnical staff for DfR Solutions. Previously, he was VP of engineering for Reactive NanoTechnologies and VP of business development for Newport Enterprises. His experience encompasses SMT manufacturing, circuit-board fabrication and materials, advanced packaging, IC fabrication processes and materials, solder reflow, RoHS, and bonding utilizing specialized nanotechnology. He is a past president of IMAPS NA, was the national chairman for the IMAPS Advanced Technology Workshop program from 1989-2000, and is the editor in chief of Advancing Microelectronics magazine. He holds a BSEE from Rutgers University and a bachelor's degree in management from St. Edwards University.

Marc Verdiell the business development leader at the Samtec Optical Group. Formerly a Bell Labs researcher and an Intel fellow, he was the founder and CEO of AlpenIO, which was acquired by Samtec in 2011. He has a PhD from the University of Paris and is the author of more than 100 peer-reviewed papers in optoelectronics.

Stephen H. Pan has worked on thermal and mechanical modeling of electronic packages since 2001 at Optimal Corp. which later became part of ANSYS/Apache in 2007. Dr. Pan is now a senior product specialist for Sentinel-TI products focusing on chip thermal simulations. Dr. Pan received his B.S. from NCKU in Taiwan (1974), an M.S. from U. of Cincinnati (1978), and a Ph.D. from Stanford University (1987), all in Mechanical Engineering. He currently serves as the secretary of the Si2 Open3D Thermal Constraint workgroup.

Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as VP and Sr. Product Strategist at Apache Design, Inc., a subsidiary of ANSYS. Prior to Apache, Dr. Chang led a group at Palo Alto HP Labs, focused on interconnect-related signal/power integrity issues and contributed to the HP-Intel IA64 micro-processor design. Dr. Chang received his B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley respectively in 1985, 1987, and 1990. He holds twelve patents and has authored over 40 technical papers. He also co-authored the popular book, "Interconnect Analysis and Synthesis", published by John Wiley & Sons, 2000. He is currently on the committee for ESDA-EDA, and Chair of the Si2 Open3D PDN workgroup.

Mr. Mark Qi Ma joined ANSYS/Apache in 2010 as a product engineer for Sentinel-TI. Prior to ANSYS/Apache, he was a thermal design engineer at Shanghai Institute of Satellite Engineering. Mr. Ma received his Master's degree in power and thermal engineering from Shanghai Chiao Tung University in 2009.

Gokul V Shankaran is a lead technical services engineer at ANSYS, working primarily on thermal modeling of electronic systems with ANSYS Icepak. Gokul has over 12 years of experience in the field of thermal management of electronics. He has driven the CAD-to-ANSYS Icepak data exchange for over 7 years. His interests include multi-physics analysis related to thermal management of electronics. Gokul received his B. Tech. from Indian Institute of Technology (IIT) Bombay in 1996, and M.S. from University of Maryland in 2000.

Dr Manoj Nagulapally received his B.Tech (Hons) degree in 1996 from the Indian Institute of Technology, Kharagpur; received his M.S. degree in 1999 and Ph.D. degree in 2001, both from the University of Minnesota, Twin Cities. He joined Fluent to work as a CFD Engineer after graduation. At Fluent and later at Ansys, he has worked in numerous roles including consulting and support services, product management and development. He currently manages the development of the electronics thermal management tool, Icepak. He has co-authored numerous journal and conference papers and has given talks at a number of universities.

Bo Yu works as an analog engineer working for Intel.

Yinglei Ren received her B.S. and M.S. degrees in electronics engineering from Shanghai Jiao Tong University, Shanghai, China in 2002 and 2005, respectively. She joined Intel in 2005 as a signal integrity (SI) engineer in Assembly and Test Technology Development (ATTD) group. She worked for Sigrity from 2007 to 2008 as an application engineer. In 2008, she rejoined Intel. And since then, she has been working as an SI engineer in Platform Engineering Group (PEG). Her area of interests includes signal integrity and power integrity.

Weifeng Shu joined Intel in 2010. He is currently a signal integrity engineer in Enterprise Platform and Service Division. Weifeng Shu received his Bachelor and Master Degrees in Beijing Institute of Technology University, Beijing, China, in 2004 and 2007 respectively. After that he joined Cisco Systems as an SI engineer till 2010.

Kai Xiao joined Intel in 2005, after receiving his Ph.D. from the EMC lab in the Missouri University of Science and Technology (a.k.a. UMR). He is a technical lead in the Platform Engineering Group (PEG), responsible for the signal integrity of high-speed serial busses on Intel Xeon® platforms. He received his B.S. and M.S. in electrical engineering from Tsinghua University, Beijing, China, in 1997 and 2000, respectively. His area of interests includes signal integrity, computational electromagnetics, power integrity, and high-speed I/O circuit design.

Romi Mayder is a senior staff signal and power integrity engineer at Xilinx, Inc. Prior to joining Xilinx, Mr. Mayder worked as a consultant specializing in silicon die level signal and power integrity. He also consulted in the field of design and fabrication of advanced package technologies, including stacked silicon interconnect. Mr. Mayder has been employed by two companies in the Test and Measurement industry, Agilent Technologies and Anritsu (Wiltron) Company, where he specialized in microwave and millimeter wave microelectronic circuit design and fabrication. Mr. Mayder has over 10 years experience in semiconductor process technologies including photolithography, ion implantation, plasma enhanced chemical vapor deposition, dielectric sputtering, and chemical mechanical polishing of silicon wafers. Mr. Mayder received his Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1992. Mr. Mayder has published 25 patent applications in the fields of signal and power integrity as well as semiconductor process technologies.

Chris Wyland is a Senior Staff Signal Integrity Engineer in the System Signal Integrity Group at Xilinx, Inc. He has over 20 years experience in package electrical modeling and signal integrity, working at such companies as Xilinx, Philips Semiconductors, and Integrated Device Technology. He has published over ten papers in the area of package signal integrity and holds over 20 patents.

Bradley Brim is Senior Staff Product Engineer in the Silicon/Package/Board division for Cadence Design Systems, Inc. His present responsibilities focus on analysis and design flow automation for power integrity and signal integrity for boards, packages and chip/package/board systems. Throughout his career he has focused on electromagnetic and circuit modeling of components, circuits and systems for SI, PI, EMC, RF, microwave and antennas. He has worked in the EDA industry for over 20 years; previously with Sigrity, Ansoft and Agilent. Brad has experience in various roles for software development, applications engineering and product marketing.

Yingxin Sun is a Senior Architect in Sigrity R&D US Group at Cadence Design System, Inc. Dr. Sun has over 12 years experience in EDA tools development for signal integrity including chip, package and board model extractions and simulations. He mainly worked on power-aware buffer modeling extraction in recent two years. He received his Ph. D from Tsinghua University, Beijing, China in Electromagnetic Theory and Microwave Technology in 1996

Lee Ritchey, founder and president of Speeding Edge, is considered to be one of the industry's premier authorities on high-speed PCB and system design. He conducts on-site private training courses for high-technology companies and also teaches courses at industry trade shows and technical conferences. Ritchey provides consulting services to top manufacturers of Internet products, such as servers, as well as other leading-edge industrial and commercial electronic-product implementations.

Paul G. Huray is professor of electrical engineering at the University of South Carolina and has worked at Oak Ridge National Laboratory, Intel, and the White House. Huray introduced the first graduate program on signal integrity and is the author of the books "Maxwell's Equations" and "The Foundations of Signal Integrity."

Dr. Priya Pathmanathan is Senior Analog Engineer at Intel Corporation where he works on observability tools development for high-speed serial and parallel busses. He develops design specifications for silicon, packaging, and platforms to enable silicon observability. He received his Ph.D. in electrical engineering from the University of South Carolina.

Dr. Steven Gary Pytel Jr. is the Lead Signal Integrity Product Manager for the Ansoft product line. He received a Doctor of Philosophy specializing in Signal Integrity from the University of South Carolina and previously worked at Intel Corporation as a Senior Signal Integrity and Hardware Design Engineer where he helped design Blade, Telecom, and Enterprise servers. His current research interests include high speed serial signaling, statistical analysis of digital circuits, and hybrid electromagnetic field solvers.

Jeff Loyer is a Signal Integrity Lead with Intel Corporation and has led much of their efforts in finding solutions for PCB issues including the Fiberweave Effect, copper roughness, and measuring and controlling insertion loss. He has spoken on these topics at past DesignCon sessions.

Richard Kunze is currently a senior staff engineer and Technical Lead in the Enterprise System Engineering (ESE) organization within the Data Center Group (DCG), Intel Corporation, DuPont, Washington. His past experience in Intel includes leading the working group responsible for signal integrity of the PCIE bus interface in Intel Server systems, research and development of passive EM structures for high speed interconnects, and advancing the development of package power delivery modeling methodology and its application to package designs for Enterprise CPU’s and chipsets. Richard Kunze received his B.S. degree in physics from the University of Rochester, Rochester, NY, in 1973 and Ph.D. in physics from SUNYAB, Buffalo, NY in 1980.

Richard Attrill is the engineering director at Polar Instruments, a UK-based company that provides design, test and measurement, and signal-integrity tools for engineers, PCB designers, and fabricators. He is extensively involved in the development of a number of products, including the Si8000m and Si9000e PCB transmission-line design systems, Speedstack stackup design and documentation system, and CGen impedance coupon generator. Attrill previously worked in the PCB fabrication industry, where he developed products for CAM, electrical test, and production planning.

Andy Burkhardt is currently Technical Marketing Specialist at Polar Instruments Ltd. Previously he has held design engineering positions at Tektronix, EDA, Qualtech and Polar Instruments with application experience in oscilloscopes, patented HDTV trigger systems, TDR metrology and introduction of the CITS family of Controlled Impedance Test Systems to the global printed circuit board manufacturing industry. Andy has previously contributed to IPC working groups on High Speed High Frequency Design (IPC2141) and TDR test methods (TM 650 2.5.5.7). He received a B.Eng (Hons) degree in Electrical and Electronic Engineering from University of Portsmouth, in 1988.

Jeff Loyer is a Signal Integrity Lead with Intel Corporation and has led much of their efforts in finding solutions for PCB issues including the Fiberweave Effect, copper roughness, and measuring and controlling insertion loss. He has spoken on these topics at past DesignCon sessions.

Gary Brist is currently a Staff PCB and Packaging Technologist working within the Integrated Platforms Research group of Intel Corporation. He received a B.S. degree in Electrical Engineering from Montana State University (1990) and his M.S. degree in Electrical Engineering from Purdue (1992). He has authored over 25 patents and 20 publications on PCB and package design focusing on the impact of material selection and fabrication. Prior to joining Intel, Mr. Brist held various engineering and engineering management positions within the PCB fabrication industry.

Richard Kunze is currently a senior staff engineer and Technical Lead in the Enterprise System Engineering (ESE) organization within the Data Center Group (DCG), Intel Corporation, DuPont, Washington. His past experience in Intel includes leading the working group responsible for signal integrity of the PCIE bus interface in Intel Server systems, research and development of passive EM structures for high speed interconnects, and advancing the development of package power delivery modeling methodology and its application to package designs for Enterprise CPU’s and chipsets. Richard Kunze received his B.S. degree in physics from the University of Rochester, Rochester, NY, in 1973 and Ph.D. in physics from SUNYAB, Buffalo, NY in 1980.

Eric Bogatin, signal integrity evangelist with Bogatin Enterprises, teaches advanced signal integrity classes worldwide. He received his bachelor of science degree in physics from the Massachusetts Institute of Technology in 1976 and his master's and doctoral degrees in physics from the University of Arizona in Tucson in 1980. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices

Yuriy Shlepnev is president and founder of Simberian, where he develops Simbeor electromagnetic signal integrity software. He received a master of science degree in radio engineering from Novosibirsk State Technical University in 1983 and a PhD in computational electromagnetics from Siberian State University of Telecommunications and Informatics in 1990. He was principal developer of an electromagnetic simulator for Eagleware and a leading developer of electromagnetic software for simulation of signal and power distribution networks at Mentor Graphics. The results of his research are published in multiple papers and conference proceedings.

Paul G. Huray is professor of electrical engineering at the University of South Carolina and has worked at Oak Ridge National Laboratory, Intel, and the White House. Huray introduced the first graduate program on signal integrity and is the author of the books "Maxwell's Equations" and "The Foundations of Signal Integrity."

Don DeGroot has more than 20 years' experience in high-frequency electrical measurements and engineering through his work in industry, government, and academia. Before launching CCN's measurement services in 2005, DeGroot directed measurement science projects at the National Institute of Standards and Technology (1993-2005); served as professor adjoint of electrical and computer engineering at the University of Colorado (1999-2005); and spent a visiting year (2002-03) at the Vrije Universiteit Brussel, where he developed a new statistical approach to network analyzer calibrations with members of ELEC. Concurrent with his CCN work, he lectures at Andrews University on instrumentation and RF. DeGroot has authored or co-authored more than 100 technical publications and presentations.

Glenn Oliver is a DuPont principal engineer responsible for characterization of electrical properties of materials for high-frequency applications. His other areas of focus are high-speed flexible circuitry interconnect and high-frequency applications support. Oliver received his bachelor of science degree in physics and his master's degree in engineering from North Carolina State University. His work background includes eight years in photonics R&D and nine years in RF/microwave development and applications.

Matt Doyle, a signal integrity engineer at IBM Corp., has 13 years' experience in 2D and 3D modeling and signal integrity working within IBM's Systems &Technology Group. One of his specialties is designing high-speed, flexible interconnect solutions for IBM Power systems, as well as for supercomputer, consumer electronics, medical, and aerospace and defense applications. The upstate New York native received a BSEE from the Rochester Institute of Technology. Doyle holds more than 50 U.S. patents in the field of electronics and flexible circuits.

Rick Brandwein is an electrical project engineer at Molex Inc., where he designs as well as performs the signal integrity testing and simulation for high-speed, high-performance flexible printed circuits. His experience includes designing electronics for automotive, military, commercial, industrial, and medical applications ranging from lithium-ion battery chargers to RF electronics and antennas. He received a BSEE from Northern Illinois University in DeKalb.

John Dangler is a development engineer at IBM with extensive experience in flex cables. He has worked in development, manufacturing engineering, and procurement positions within IBM. Today he is responsible for design, qualification, sourcing, and quality engineering for flex and rigid-flex implementations. Applications have included medical, military, consumer, servers, and supercomputers. Dangler graduated from Clarkson College with a bachelor of science degree in chemical engineering. He has 18 patents issued or filed related to electronic packaging.

Aldo Morales has a PhD in electrical and computer engineering from the State University of New York at Buffalo. He has been involved in teaching signal processing, microprocessors, software applications, and local area networks for many years. Morales received an Engineering Society Outstanding Teaching award from the Pennsylvania State University College of Engineering and an Educator of the Year award from Penn State DuBois; was funded through the College of Engineering and IEEE Mountain Section (PA) to develop a modern LAN; and was instrumental in developing an advanced computer laboratory for the EET and IST programs at Penn State DuBois with grants from the Shared University Research Grant, IBM. Morales is the PI for a three-year Ben Franklin Technology Partners Grant that established the Center of Excellence in Signal Integrity at Penn State Harrisburg and has won a number of best-paper awards.

Sedig S. Agili has a PhD in electrical and computer engineering from Marquette University. In addition to a wealth of teaching experience, including courses and laboratories in electronic communications, network analysis, fiber optics, electronics, and electromagnetic fields, Agili has industrial experience, having designed optical projection and heads-up display systems. From 2001 to present, he has been involved in supporting and consulting local connector companies in signal integrity. He was the PI for the grant from the Pennsylvania State University, "High-speed Signal Integrity Research Related to Communications Link Components," and Co-PI for the three-year Ben Franklin Technology Partners Grant that established Penn State Harrisburg's Center of Excellence in Signal Integrity. He was a co-author for the Best Poster Paper award at the IEEE International Conference on Consumer Electronics 2007 for the paper "Transmitter Pre-emphasis and Adaptive Receiver Equalization for Duobinary Signaling in Backplane Channels."

Mike Resso is a signal integrity application scientist in the Component Test Division of Agilent Technologies and has more than 25 years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high-speed digital interconnects using time-domain reflectometry and vector network analysis. He has authored more than 30 professional publications, including a book on signal integrity. Resso has been awarded one U.S. patent and has twice received the Agilent Spark of Insight Award for his contribution to the company. He received a bachelor of science degree in electrical and computer engineering from the University of California.

Jeff Clark is an electrical engineering undergraduate student. He did his undergraduate internship at the Center for Signal integrity at the Pennsylvania State University Harrisburg.

Chris Kocuba was an Electrical Engineering undergraduate student. He did his undergraduate internship at Center for Signal integrity at Penn State Harrisburg. Chris now works in Samtec, a connector company in the Harrisburg, PA area.

Kai Keskinen is design engineering manager at Celestica International Inc. Keskinen joined CoreSim in 2003 to lead the signal integrity team. CoreSim was purchased by Celestica in 2005. Keskinen leads the Celestica SI team in performing analyses on Celestica's internally developed products and for Celestica's manufacturing customers. Before Celestica, he was with Nortel Networks, C-MAC Engineering, and Solectron, performing EMC/EMI and SI work. He holds a BSc degree in applied math and physics and PhD in experimental space science from York University.

Vance Bolling is team lead for the CoreSim Schematic Modeling team at Celestica. He has been part of the CoreSim team since 2004. Before Celestica, he was a test engineer at Nortel Networks. Bolling holds a BSc degree in biological engineering and a BASc in electrical engineering.

Geoff Liu is design engineering manager for the CoreSim team at Celestica. He joined CoreSim in 2004, and has worked as part of the signal integrity, FPGA, and board design teams. Before Celestica, he was a hardware designer at Alcatel and Newbridge Networks. He holds a BASc in electrical engineering.

Xiang Li is a senior hardware engineer at Intel Corp. He received his PhD from the University of Massachusetts Lowell. He has broad interests and experience in interconnect design, analysis , validation, and signal-integrity solutions for Intel platforms, ans is heavily involved in DDR4 memory connector standardization through JEDEC.

Per Viklund is director of RF and IC packaging at Mentor Graphics and a longtime IEEE & IMAPS member with more than 30 years of experience in electronic design and development of advanced EDA tools. He has won several industry awards for delivering groundbreaking technology. As a recognized industry expert in advanced packaging and RF design, he has published and presented numerous papers on IC packaging, embedded components, RF, and high-speed design. Before joining Mentor in 2003, Viklund was chief technical manager of DDE-EDA for 10+ years.

Istvan Novak is a senior principal engineer at Oracle Corp. Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of power-distribution networks and packages for midrange servers. He creates simulation models and develops measurement techniques for power distribution. Novak has more than 20 years of experience with high-speed digital, RF, and analog circuit and system design. He has been made an IEEE fellow for his contributions to signal integrity and RF measurement and simulation methodologies.

Ying Li is a Hardware Engineer at Oracle Corporation where she works on signal and power integrity of ASIC packaging interconnects simulation and measurement validation. In previous graduate studies, her research work focused on computational electromagnetics, sensitivity analysis and optimization. She received her Masters degree in electrical engineering from McMaster University. She is pursuing her Ph.D. degree at University of Washington.

Eben Kunz graduated from MIT in 2012 with a BS and Master's in EE. His thesis project was the design and construction of analog processing components for a low frequency radio telescope. He joined Oracle in May 2012, and has been working on simulation and modeling of high-speed interconnects.

Sarah Paydavosi is a hardware engineer at Oracle Corp. Her current work focuses on signal integrity modeling, analysis, and validation in Oracle's MicroElectronics ASIC and SoC IP group. She received her PhD in electrical engineering from Massachusetts Institute of Technology.

Laura Kocubinski is a hardware engineer at Oracle Corp. Currently, she works on signal integrity within Oracle's SPARC T-Series server division. She received her BSEE, with a technical concentration in communications and information processing, from Rensselaer Polytechnic Institute in 2012.

Kevin Hinckley is a Principal Signal Integrity Engineer at Oracle with more than 15 years in the industry. Kevin has spent the last 12 years at Oracle in various product design groups and is currently responsible for all aspects of signal integrity modeling, analysis and validation for Oracle's x86 based servers. Before Oracle, Kevin worked in the Defense Industry with a focus on semiconductor device modeling, simulation and measurement. He received a BSEE from Rensselaer Polytechnic Institute.

Alexander Nosovitski is a Principal Signal Integrity Engineer at Oracle Corporation with more than 12 years in the industry. Alex has spent the last 8 years at Oracle and is currently responsible for signal integrity modeling, analysis and validation for Oracle's x86 based servers. He received a BSEE from Northeastern University and MSSE from Brandeis University.

Nathaniel Shannon is a Signal Integrity Hardware Engineer at Oracle Corporation. He is responsible for the development of signal integrity modeling and simulations of high speed serial and parallel buses as well as simulations of power distribution networks. He received his M.S. from Northeastern University.

Gustavo J. Blando is a Principle Hardware Engineer with over ten years of experience in the industry. Currently at Oracle Corporation, he is responsible for the development of new processes and methodologies in the areas of broadband measurement, high speed modeling and system simulations. He received his M.S. from Northeastern University.

Jongbae Park is a staff signal integrity engineer in the Hard IP Division of the Intel Architecture Development Group. He is currently leading projects for simulation and measurement correlation/methodology in both high-speed serial-link and DDR memory channels. He is also responsible for LPDDR3 and LPDDR4 electrical specification development at Intel. Previously, he worked for Silicon Image, where he was responsible for the EMI, signal integrity analysis, modeling, simulation, and measurements for HDMI, SATA, and MHL links. He holds a PhD electrical engineering from Korea Advanced Institute of Science and Technology. He has more than 30 publications in refereed journals and conferences, and five issued patents. He has also served as a reviewer of IEEE Transactions on EMC, Advanced Packaging, and MTT.

Qin Li is a manager with the Memory Signal Integrity Group in the Hard IP Division of the Intel Architecture Development Group.

Myunghyun Ha is a senior signal integrity engineer in Hard IP Division of Intel Architecture Development Group, Intel Corporation. He is working on signal integrity in various memory interfaces and memory specification developments. He received his Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology in 2011.

Kyoung-Hoi (Billy) Koo, a principal engineer at Samsung Electronics, received bachelor's and master's degrees in electrical engineering from Chungbuk National University, South Korea, in 1996 and 1998, respectively, with a focus on high-speed I/O transceivers. In 1998, he joined Samsung Electronics, where initially he designed and developed high-speed peripheral interfaces such as PCI-X, AGP, HSTL, SSTL, LVDS and USB2.0. From 2004 to the present, he has been responsible for developing high-speed memory interface circuits for DDR2/DDR3/DDR4 and LPDDR2/LPDDR3. He holds more than 10 U.S. and foreign patents, and he has published six papers and conference contributions in analog/digital mixed-signal design and high-speed interface areas.

Sangmin Lee leads SoC/AP platform integrity and electrical validation as a principal engineer at Samsung Electronics. He has been responsible for I/O platform enabling activities and design methodology development for high-speed memory and serial interfaces. Before Samsung, Lee worked as a senior component design engineer at Intel Corp., where he developed tests and tools for system validation of chip sets and processors.

Scott Best is a senior principal engineer in the Rambus Labs organization, where he works in memory architecture research. He has more than 40 issued patents in areas of integrated circuit design, advanced signaling, next-generation memory systems, and 3D packaging. Best received his BSEE degree from Cornell University in 1989.

Dave Secker is a technical director in systems engineering at Rambus Inc., where his responsibilities include physical design, modeling, and optimization of high-speed signal interconnect and power delivery networks at the IC package and system board levels. Previously, he worked at Los Alamos National Laboratory as a research assistant. Secker received his master's degree in electrical and computer engineering from the University of Arizona in 1996.

Thomas Giovannini is a senior principal engineer in the architecture organization at Rambus Inc., where he is currently focused on low-power mobile memory PHY architecture. His extensive hardware development experience before Rambus includes high-speed test equipment and computers, digital radio communication systems, telecommunications systems, and optical communication systems. He received a BSEE degree from the University of California, Berkeley in 1981 and an MSEE degree from Santa Clara University in 1988.

Don Mullen is a senior principal engineer at Rambus Inc., where he focuses on systems mechanical and thermal design. He has been at Rambus for the past 14 years. He has a BSME and is a California PE in mechanical engineering. Prior to Rambus, he held various technical positions involving electronic packaging, thermal design, biomedical engineering, and mechanical systems engineering design. Previous affiliations include Acuson Corp., Evans & Sutherland, Amdahl Corp., UC Lawrence Labs, SFBARTD, consultancies in industrial control and rail transportation, and Pacific Car and Foundry Inc.

Ming Li has been a packaging engineer at Rambus Inc. since 2000. He is responsible for advanced IC packaging development, IC package design and substrate layout, and thermal and mechanical analysis of IC packages. Previously, he worked at Sandia National Lab as a research associate, at Tessera Inc. as a modeling engineer, and at PerkinElmer Inc as a senior packaging engineer. He holds bachelor's, master's, and doctoral degrees in materials science and engineering.

Arun Vaidyanath is a director of system engineering at Rambus Inc. responsible for delivering system solutions and platforms for the validation of Rambus high-speed I/O and memory interfaces. His team has developed system platforms for high-volume products in the gaming and consumer spaces (e.g., Playstation3, digital televisions and DLP projectors). He has more than 16 years of experience in the areas of signal integrity and system engineering. He holds a B.Tech. in electronics engineering and an MS in electrical and computer engineering from the University of Arizona, and has authored several papers and publications in leading technical conferences and journals in signal integrity and system engineering.

Dan Oh is currently responsible for driving the overall SI/PI technical direction at Altera Corp. as well as leading the IC product development SI/PI team. He was most recently a technical director at Rambus Inc., where he defined the signaling road map, supported system definition of new product proposals, and drove IP development for innovative signaling solutions. He has more than 20 years' experience in signal and power integrity. Oh received his PhD in electrical engineering from the University of Illinois at Urbana-Champaign. He has numerous patents and papers in the areas of high-speed I/O modeling, simulation, and design. He is the lead author of the book "High-speed Signaling: Jitter Modeling Analysis, and Budgeting" and serves on the technical program committees of leading conferences such as IEEE EPEPS, IEEE ECTC, and DesignCon.

Yohan Frans is a senior engineering manager at Rambus Inc. Since joining Rambus in 2001, he has worked on high-speed serial links, high-performance memory interfaces, and mobile memory interfaces. His current interests include high-speed signaling, clocking circuits and architectures, transmitter and receiver circuits, and low-power design and methodology. He received his bachelor of science degree in electrical engineering from Bandung Institute of Technology, Indonesia, in 1995 and his master of science degree in electrical engineering from Stanford University in 2001.

John Ellis is a Synopsys Inc. principal engineer specializing in system-level signal integrity analysis. He joined Synopsys in August 2005. Ellis was a co-founder of TriCN, a semiconductor IP company based in San Francisco. He has authored several patents in the field of high-speed interconnect.

Chanmin Jo is a senior engineer at Samsung Electronics, having joined the company in 2006. He is responsible for the development of modeling and analysis for high-speed memory interfaces. He received bachelor of science and master of science degrees in electrical engineering from Hanyang University, South Korea, in 2004 and 2006, respectively, with a focus on modeling and characterization for signal integrity of high-speed integrated circuits, IC interconnect, and IC packaging.

Baek-Kyu Choi is a signal integrity engineer at Samsung Electronics Inc. He is working on signal and power integrity analysis for memory module and on-board memory development. His interests include on-chip and off-chip signal integrity, power integrity, system optimization, and high-speed digital circuit design. He received his bachelor's and master's degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejeon, South Korea).

Sangmin Lee leads SoC/AP platform integrity and electrical validation as a principal engineer at Samsung Electronics. He has been responsible for I/O platform enabling activities and design methodology development for high-speed memory and serial interfaces. Before Samsung, Lee worked as a senior component design engineer at Intel Corp., where he developed tests and tools for system validation of chip sets and processors.

Seungbae Lee is with Samsung Electronics and works on electromagnetic interference/susceptibility qualification as a senior engineer in the Technology Quality and Reliability group. His current research interest is the power distribution network impedance specification. He received his bachelor's degree in electronics and communication engineering from Kwangwoon University, Seoul, in 1996 and his master's degree semiconductor systems engineering from Sungkyunkwan University, Suwon, South Korea, in 2009.

Yonghoon Kim joined Samsung Electronics in 2006 and is currently leading an electrical modeling and simulation of a package part.

Seongjae Moon, a senior engineer at Samsung Electronics, received BS and MS degrees in control and Instrumentation engineering from Kwangwoon University, South Korea, in 1999 and 2001, respectively. He has been responsible for enabling high-speed memory interfaces and verifying the functionality of SoCs and APs at Samsung Electronics. Before joining Samsung, he worked as a system programmer at Navicom, where he developed GPS chip sets and receivers.

Minho Seo has been responsible for enabling high-speed memory and serial interfaces and developing boards for signal and power integrity as a Samsung Electrronics senior engineer. Seo received a bachelor of science degree in electrical engineering from Soongsil University, South Korea, in 2001.

Jonghyun Cho received B.S. and M.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2008 and 2010, respectively. He is now a Ph.D. candidate in electrical engineering from KAIST. His research interests include Si-interposer design, TSV noise coupling, and TSV depletion effects in TSV-based 3D IC.

Joohee Kim (S'09) received her bachelor's and master's degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejeon, South Korea) in 2008 and 2010, respectively. She is currently pursuing a PhD degree in electrical engineering from KAIST. Her research interests include TSV modeling and failure analysis in TSV-based 3D ICs.

Hyun-Cheol Bae received the B.S. and M.S. degrees in electrical engineering from Dongguk University, Seoul, Korea, in 1999 and 2001, respectively, and the Ph.D. degree in electrical engineering from Chungnam National University, Daejeon, Korea, in 2009. He joined the SiGe Research Team, Electronics and Telecommunications Research Institute (ETRI) Daejeon, Korea, in 2001, as a Design and Process Engineer for MMIC and passive devices. He joined the Package Research Group, ETRI, in 2008, as a Packaging Engineer. His current research interests include 3-D stacked chip packaging using through-silicon-via and microelectromechanical systems wafer level packaging.

Kwangseong Choi received the B.S. degree from Hanyang University, Seoul, Korea, and the M.S. and Ph.D. degrees from the Korea Advanced Institute of Science and Technology, Daejeon, Korea. He was engaged in development of chip scale packages, PoP packages, and designed high-speed electronic packages for DDR, Rambus, and RF devices with Hynix Semiconductor, Inc., Seoul, from 1995 to 2001. He has been involved in development of high-speed packaging technologies for optical devices such as modulators and receivers, since 2001, with the Electronics and Telecommunications Research Institute (ETRI), Daejeon. He is the Team Leader of the Package Research Team, ETRI. His current research interests include the development of the materials and processes for 3-D integrated circuits with through-silicon-via.

Seungwook Paek received the B.S. and M.S. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2009 and 2010 respectively, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interests include computer-vision-inspired thermal analysis algorithm and its on-chip implementation.

Lee-Sup Kim received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1982, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1986 and 1990, respectively. He was a Post-Doctoral Research Fellow with Toshiba Corporation, Kawasaki, Japan, from 1990 to 1993, where he was involved with the design of the high-performance digital signal processor and single-chip MPEG2 decoder. Since March 1993, he has been with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, where he became a Professor in September 2002. He is currently with the MVLSI Laboratory, Department of Electrical Engineering, KAIST. In 1998, he was on sabbatical leave with Chromatic Research and SandCraft, Inc., Sunnyvale, CA. His current research interests include 3-D graphics processing unit design and high-speed/low-power mixed-mode integrated circuit design.

Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and a Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. He is currently a Professor at the Electrical Engineering and Computer Science Department. Since joining KAIST, his research has centered on modeling, design, and measurement methodologies of hierarchical semiconductor systems including high-speed chip, package, interconnection, and multi-layer PCB. Especially, his major research topic is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity, and radiated emission in 3D semiconductor packages, system-in-package(System-in-package), and SoP(System-on-package). He was on a sabbatical leave at Silicon Image Inc., Sunnyvale CA, as a staff engineer during the 2001 to 2002 academic year. He was responsible for low noise package design of SATA, FC, HDMI, and Panel Link SerDes devices. Currently, he is the director of the Satellite Research Laboratory of Hyundai Motors for EMI/EMC modeling of automotive RF, power electronic and cabling systems. He has more than 210 publications in refereed journals and conferences. Dr. Joungho Kim has been the chair or the co-chair of the EDAPS workshop since 2002. Currently, he is an Associated Editor of the IEEE Transactions of Electromagnetic Compatibility.

Michael Steinberger, lead architect at SiSoft Inc., has more than 30 years' experience in the design and analysis of very high-speed electronic circuits. He is currently responsible for the architecture of SiSoft's Quantum Channel Designer tool for high-speed serial channel analysis. He started his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high-speed digital backplanes used throughout Lucent's transmission product line. Before joining SiSoft, Steinberger led a group at Cray Inc., performing SerDes design, high-speed channel analysis, PCB design, and custom RAM design. He holds a PhD from the University of Southern California and has been awarded 14 patents.

Eric Brock, principal member of the technical staff at SiSoft Inc., works closely with customers and semiconductor vendors involved in the design and analysis of multi-gigahertz serial links. He has analyzed dozens of high-speed parallel and serial interfaces since joining SiSoft in 2002. Prior to SiSoft, he worked at Compaq Computer as a signal entegrity engineer in the Alpha Development Group. He received his BS in electrical engineering and a BS in physics from Portland State University in 1998.

Donald Telian is an independent signal integrity consultant. Building on more than 25 years of SI experience at Intel, Cadence, Hewlett-Packard, and others, his recent focus has been on helping customers correctly implement today's multi-gigabit serial links. His numerous published works on this and other topics are available at his Web site, siguys.com. Telian is widely known as the SI designer of the PCI bus and the originator of IBIS modeling and has taught SI techniques to thousands of engineers in more than 15 countries.

Xiaoxiong (Kevin) Gu is a research staff member at IBM's Thomas J. Watson Research Center. His research interests include characterization of high-speed interconnect and microelectronic packaging, signal integrity, and computational electromagnetics. He received his bachelor of science degree from Tsinghua University, Beijing, in 2000; master's degree from the University of Missouri-Rolla in 2002; and PhD from the University of Washington, Seattle, in 2006, all in electrical engineering.

Young H. Kwark received his BSEE from the Massachusetts Institute of Technology and his MSEE/PhD from Stanford University. His work experience as a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, includes circuit design for optical links and wireless applications. He is currently involved in package characterization for high performance computing platforms. Dr. Kwark is the recipient/co-recipient of DesignCon Paper Awards in 2005, 2006, 2008 and 2010.

Christian W. Baks joined the IBM T.J. Watson Research Center as a staff engineer in 2001. Baks is involved in high-speed optoelectronic package and backplane interconnect design, specializing in signal integrity issues. He received a bachelor of science degree in applied physics from Fontys College of Technology, Eindhoven, Netherlands, in 2000 and a master of science degree in physics from the State University of New York at Albany in 2001.

Lei Shan joined the IBM T.J. Watson Research Center in January 2000 as a research staff member. At IBM, he works on high-speed electronics and optoelectronics packaging design as well as electrical and thermal simulations. He designed and demonstrated a high-speed package for a 50-Gbps multiplexer and demultiplexer based on IBM SiGe BiCMOS technology. Shan received a bachelor of science degree in mechanical engineering from Zhejiang University, China, in 1986 and a master's degree in electrical engineering and PhD in mechanical engineering from the Georgia Institute of Technology in 2000. From 1997 to 2000, as grad student, he studied the tribological aspects of the chemical mechanical polishing process for microelectronics fabrication. Shan has authored more than 20 papers and patents.

Xiaomin Duan is a postdoctoral research assistant in the Institute of Electromagnetic Theory at Technical University Hamburg-Harburg. His research interests include application and extension of the method of moments to the electrical analysis of printed-circuit boards in high-speed digital systems. Duan received a bachelor of science degree in electrical engineering from China's Zhejiang University in 2002. At Technical University Hamburg-Harburg, he earned a master of science degree in microelectronics and microsystems in 2007 and a PhD in electrical engineering in 2012.

Sebastian Mueller is a research assistant with the Institute of Electromagnetic Theory at Technical University of Hamburg-Harburg, working toward his PhD. His main focus is on via arrays in multilayer substrates. Mueller received his bachelor of science degree in general engineering science and diploma degree in electrical engineering from Technical University of Hamburg-Harburg in 2007 and 2009, respectively, and an MBA in technology management from the Northern Institute of Technology Management in Germany in 2009.

Christian Schuster has been a full professor and head of the Institute of Electromagnetic Theory at Germany's Technical University of Hamburg-Harburg since 2006. Before that, he was with the IBM T.J. Watson Research Center, where he was involved in high-speed optoelectronic package and backplane interconnect modeling and signal integrity design for new server generations. His current interests include signal and power integrity of digital systems, multiport measurement and calibration techniques, development of electromagnetic simulation methods, and the electromagnetic compatibility problems of communication electronics. He received a diploma degree in physics from the University of Konstanz, Germany, in 1996, and a doctoral degree in electrical engineering from the Swiss Federal Institute of Technology, Zurich, in 2000.

Thomas-Michael Winkel is an advisory engineer and the technical lead for z10 midrange systems at IBM's Thomas J. Watson Research Center. His focus is electrical packaging design with respect to signal integrity, power integrity, and system aspects. He received both his diploma and doctoral degrees in electrical engineering from the University of Hannover, Germany. He has authored or coauthored more than 20 conference and journal papers and holds 10 patents. Winkel was general co-chairman of the IEEE European Systems Packaging Workshop 2009 and is a technical program committee member of the Electrical Performance on Electronic Packaging and the Signal Propagation on Interconnects Workshops.

Thomas Strach joined IBM in 1997 and then joined the IBM Systems and Technology Group in 2004 as a staff engineer. His main responsibility is the power decoupling design of IBM high-end servers. His current fields of interest include the simulation and experimental verification of on-chip power noise propagation as well as the design of guidelines for the effective placement of on-chip decoupling cells. Strach received a master of science degree from Canada's McMaster University in 1992 and a PhD in physics from the University of Stuttgart, Germany, in 1997.

Hubert Harrer is a senior technical staff member at IBM Research and Development. He has been the technical lead for zSeries central electronic complex packaging designs since 2001. His technical interests focus on packaging technology, high-frequency designs, and electrical analysis for first- and second-level packaging. Harrer received his diploma and doctoral degrees in electrical engineering, both from the Technical University of Munich. He has published multiple papers and holds 12 patents in the area of packaging.

Renato Rimolo-Donadio joined the IBM T.J. Watson Research Center in 2012 as a postdoctoral researcher. From 2006 to 2011, he was with the Institute of Electromagnetic Theory at the Technical University of Hamburg-Harburg, Germany. His current research interests include system-level modeling and optimization of interconnects, and analysis of signal and power integrity problems at the PCB and package levels. Rimolo-Donadio received his bachelor's and license degrees in electrical engineering from the Technical University of Costa Rica, Cartago, in 1999 and 2004, respectively, and his master's degree with distinction in microelectronics and microsystems and doctoral degree summa cum laude in electrical engineering from the Technical University of Hamburg-Harburg in 2006 and 2010, respectively.

Xingdong Dai is a system engineer in the serial interface and protocol solution group at LSI Corp. Since 2008, he has been working on SerDes modeling, software development, and applications. Previously, he was involved with mixed-signal design at Agere Systems (now LSI), FPGA design at Spinnaker Networks (now NetApp), and custom IC design at Lucent Technologies. Dai received a PhD in computer engineering from Lehigh University and holds MSEE and BSEE degrees from Arizona State University and Southern Illinois University at Carbondale, respectively.

Fangyi Rao is a master R&D engineer for Analog/RF Simulation and Signal Integrity at Agilent Technologies, Santa Clara. He joined Agilent EEsof in 2006 and works on analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006, he was with Cadence Design Systems, where he made key contributions to the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Earlier, he worked in the areas of EM simulation, nonlinear device modeling, and optimization. Rao received a PhD in theoretical physics from Northwestern University in 1997.

Shiva Prasad Kotagiri is a systems engineer for high-speed SerDes transceiver design at LSI Corp. in Milpitas, CA. He received his master of science and doctoral degrees in electrical engineering from the University of Missouri-Rolla and University of Notre Dame in 2003 and 2008, respectively. He was with Xilinx Inc. from 2008 to 2011 as a systems engineer for high-speed SerDes transceiver design.

Cathy Ye Liu heads up LSI Corp.'s SerDes Architecture group as distinuished engineer. Since 2002, she has been working on high-speed SerDes solutions. Previously, she developed read channel and mobile digital TV receiver solutions. She received her bachelor of science degree in electronic engineering from Tsinghua University, China, in 1995 and received her master's and doctoral degrees in electrical engineering from the University of Hawaii in 1997 and 1999, respectively. Her technical interests are signal processing and coding in high-speed SerDes.

Mahbubul Bari, senior IC modeling engineer at Maxim Integrated Products, has worked in the semiconductor industry for more than 23 years. His recent experience includes high-speed channel design, SI simulation, modeling, verification, and validation of SerDes, redrivers, and retimers for multi-gigahertz links. Bari received his master of science degree in electrical engineering from the University of Colorado and his BSEE from Wichita State University. He participated in the SAS2 and SAS3 T10 PHY Working Group in support of the 6G and 12G physical-layer initiative, and developed IBIS-AMI models for SAS-2 and SAS-3 reference TX and reference RX.

Ron Olisar, principal member of the technical staff at Maxim Integrated Products, received his master of science degree in electrical engineering from Stanford University and his bachelor of science degree from Carnegie Mellon University. During 20 years at Tektronix, Olisar architected real-time digital oscilloscopes and pipelined digitizer chip sets, and managed the development of telecommunications test equipment (SONET/SDH Test, nQAM CATV, and CDMA BTS Test). He joined Maxim in 2000 and is a product definer of backplane and cable signal integrity redriver/repeater solutions for 1- to 28-Gbps datacom, telecom, and digital video applications.

Hassan Rafat, principal member of the technical staff for IC modeling at Maxim Integrated Products, received his PhD in microelectronics from the University of Edinburgh, U.K., in 1983. As a visiting assistant professor, Rafat conducted research and taught at Texas A&M University during 1983 and 1984. Subsequently, he joined semiconductor companies including American Microsystems, Exar Corp., and National Semiconductor. He joined Maxim Integrated in 2005. He has a number of technical publications in the fields of sampled-data analog integrated filters and DSP algorithms and coding for modem applications.

Fangyi Rao is a master R&D engineer for Analog/RF Simulation and Signal Integrity at Agilent Technologies, Santa Clara. He joined Agilent EEsof in 2006 and works on analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006, he was with Cadence Design Systems, where he made key contributions to the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Earlier, he worked in the areas of EM simulation, nonlinear device modeling, and optimization. Rao received a PhD in theoretical physics from Northwestern University in 1997.

Ming Yan joined Agilent EEsof in 2006 as a software R&D engineer and works on device modeling and simulation technologies in ADS and RFDE. His most recent contributions are in the field of SI simulation technologies in ADS. Yan eceived his PhD in electrical engineering from Illinois Institute of Technology in 2005 for research on EM simulation and semiconductor device modeling. Recent publications include "Rigorous Modeling of Transmit Jitter for Accurate and Efficient Statistical Eye Simulation," DesignCon 2010, Track 8-TP2.

Sharon Wang is a principal member of the technical staff at Maxim Integrated Products, where she has been working on product definition in the areas of optical transceivers, signal integrity, SerDes, CDRs, and low-jitter clock synthesizer products. Recently she got involved in SI simulation using different EDA tools. She received her PhD degree in applied science (optical communication and broadband access networks) from the University of Gent, Belgium, in 1998.

Chad Morgan is a senior principal engineer at TE Connectivity, where he focuses on high-frequency measurement and characterization of components and materials, full-wave electromagnetic modeling of high-speed interconnects, and the simulation of digital systems. He is a Distinguished Innovator with numerous patents at TE Connectivity, and he has presented multiple papers at trade shows such as DesignCon and the International Microwave Symposium. He earned his degree in electrical engineering from the Pennsylvania State University in 1995.

Adam Healey is a distinguished engineer at LSI Corp., where he supports the development and standardization of high-speed serial interface products. During his tenure at Lucent Microelectronics, which later became Agere Systems and then LSI, he was involved in channel modeling and equalization strategies for high-speed optical and electrical links, transcoding and error correction coding subsystems, and transport networking architecture. Healey is a regular contributor to the development of industry standards through his work in the IEEE 802.3 Ethernet Working Group and INCITS T11.2 Fibre Channel Physical Variants Task Group. He was chairman of the IEEE P802.3ap Task Force chartered to develop the standard for Ethernet operation over electrical backplanes at speeds of 1 and 10 Gbps. He is currently secretary of the IEEE 802.3 Ethernet Working Group and chief editor for the IEEE P802.3bj 100 Gb/s Ethernet over Backplane and Copper Cable Task Force. He received bachelor of science and master of science degrees in electrical engineering from the University of New Hampshire in 1995 and 2000, respectively.

Megha Shanbhag is a signal integrity engineer at TE Connectivity, where she has been working for the past five years. Her work includes design and analysis of high-speed components, full-wave electromagnetic modeling and validation of high-speed interconnects, and simulation of high-speed links. She is also a regular participant and contributor at the IEEE 802.3 Ethernet Working Group meetings. She received her BSEE degree from the University of Mumbai in 2005 and her MSEE from Drexel University in 2007.

Jenny Xiaohong Jiang is a senior member of the technical staff at Altera Corp., where her primary focus is on high-speed, high-performance die/package/PCB co-design and technology development. Her responsibilities include package transceiver channel design; investigations of 3D interposer TSV effects; and analysis of PDN noise, SSN, and jitter. Before Altera, she was with Lucent Technologies and BigBear Network, working on package modeling and 40-Gbps transponder package design. She holds an MS degree from Ecole Polytechnique de Montreal in the area of RF and microwave technologies. She has authored and co-authored more than 20 technical papers and published two patents, with six others pending.

Hong Shi is a senior manager at Altera Corp., overseeing system-level interconnect and packaging designs. He has worked at Altera for more than seven years as a design engineer, electrical design manager, and packaging senior manager. Before Altera, he led the introduction of the first 40-GHz analog module in Agilent's Infiniium DCA series. He has more than 20 years of industry and research institute experience in optoelectronics, optical fiber communication, microwave circuits, and digital circuit packaging. He has published more than 50 technical articles in various peer-reviewed IEEE journals and international conferences, as well as one book chapter, and holds 15 issued and pending patents in related fields. He holds a PhD in optics and photonics from the College of Optics and Photonics at the University of Central Florida, and MSEE and BSEE degrees from Xi'an JiaoTong University, China.

Siow Chek Tan is an Altera Corp. electrical design engineer responsible for package development across the wirebond and flip-chip product lines. She joined Altera in 2007 and has published four papers at Altera symposia and IEEE conferences. Her areas of interest are signal integrity and high-speed SerDes channel design. She received her BSc (with honors) degree in electrical engineering from the University of Technology, Malaysia.

Joe Sanchez is currently an Altera Corp. engineer and has been a participant in the semiconductor industry since 1983. He has 13 years of FA experience. His current responsibilities include die- and package-level physical failure analysis, including X-section, parallel lap, deprocess, decap, SEM/FIB/optical inspection, and FA lab management.

Yuri Tretiakov is a senior member of the technical staff at Altera Corp. He received his MS degree in electrical engineering from the Moscow Institute of Physics and Technology and his PhD in electrical engineering from Arizona State University, Tempe. Currently, he is working on power delivery network characterization, high-speed hardware evaluation, and the design of FPGA characterization boards. He has authored or co-authored 35 journal and conference papers. He also published a book chapter and has two U.S. patents issued.

June Feng is a member of the technical staff at Altera Corp., where she is is responsible for channel VT budget simulation and high-speed channel characterization. She joined Altera in 2011 and earlier worked at Amkor and Rambus. She has been involved in performing detailed analysis, modeling, design, and characterization in a variety of areas, including high-speed, low-cost PCB layout and device packaging. Her interests include high-speed interconnects modeling, channel VT budget simulation, power delivery network modeling, and high-frequency measurements. She received her master of science degree from the University of California, Davis, and her bachelor's degree from Beijing University.

Ed Frlan is a senior system architect within the Gennum Products Group of Semtech Corp., responsible for the definition of next-generation 28-Gbps products. Frlan is OIF PLL Interoperability Working Group chair and has contributed to the development of the CEI-28G-VSR Implementation Agreement. He joined Gennum from a hardware architect position within the Metro Ethernet Networks division of Ciena, where he was responsible for the system architecture and synchronization aspects of various line cards (including Carrier Ethernet, SONET, OTN and Broadcast Video). Ed is actively participating in the OIF Physical and Link Layer working group and holds a PhD in electrical engineering from Carleton University.

Francois Tremblay is vice president of design engineering for the Gennum Products Group of Semtech Corp., responsible for the development of 8- to 25-Gbps module retimer and backplane products. Before Gennum, Tremblay held positions from manager to VP at Nortel, Cadence, Catena Networks, Ciena, and LTRIM technology. His expertise in communications ranges from discrete multitone modulation on twisted pair to QAM on cable modem and 28-Gbps NRZ for module and backplane applications. He holds a bachelor of science degree in electrical engineering from the University of Ottawa.

Richard Mellitz is a principal engineer in the Platform Engineering Group at Intel Corp. His expertise in platform signaling architecture has facilitated leadership of signal integrity for Intel servers. Mellitz has been a key contributor for the channel sections of the 10-, 40-, and 100 Gbps IEEE802.3 backplane standards. He founded and chaired the IPC committee that deliverd IPS's first PCB loss test method. Mellitz wrote the original IPC TDR standard, which is used throughout the PWB industry. He holds a number of patents in signal integrity, design, and test and has delivered many signal integrity papers at PC industry design conferences.

Adee Ran received the B.S degree in electrical engineering in 1991 and the M.S degree in electrical engineering in 2000, both from the Israel Institute of Technology (Technion). From 1991 to 2003 he was an R&D engineer at the Israel Defense Forces (IDF). In 2003 he joined the LAN Access Department at Intel in Haifa, Israel, where he works as a PHY architect for high-speed serial communication technologies, including Ethernet, PCI Express, and Thunderbolt. Adee is a member of the IEEE and an active contributor to the IEEE 802.3 Ethernet working group. He holds four U.S. patents.

Dr. Li has been with Altera Corporation 2007 and currently is an Altera Fellow. He is a corporate expert and adviser, as well as CTO office principal investigator, on high-speed link technology, standard, SERDES architecture, electrical and optical signaling, silicon photonics, optical FPGA, high-speed simulation/debug/test, jitter, noise, signal and power integrity. He was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007. Dr. Li is a Fellow of IEEE, and an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle. He holds a Ph.D. in physics (1991), an M.S.E (1991), in electrical and computer engineering and an M.S. in physics (1987), from the University of Alabama, Huntsville. He also holds a B.S (1985) in space physics from the University of Science and Technology of China. He was a Post Dr. and then a research scientist at the University of California, Berkeley (1991-1995).

Mike Jenkins, senior staff design engineer at Xilinx Inc., received a bachelor of science degree in electrical engineering and a master's degree in mathematics from the University of Illinois, Urbana as well as an MSEE from Syracuse University. During his 37-year career, he has held engineering positions at IBM (Data Systems and General Products Divisions), LSI Corp., and Xilinx, with a primary focus in the areas of signal integrity and SerDes design and analysis. He holds 16 patents.

David Mahashin is Staff Systems Applications Engineer for Xilinx’s SERDES group. He received his BS and MS in Electrical Engineering from Stanford University. He has been at Xilinx for the past 5 years, focusing on IC design and high-speed transceiver characterization.

Xin Wu is a senior electrical engineer in the Connector Product Division at Molex Inc. His industry experience includes electromagnetic simulation/EDA software development, EMC/EMI engineering, signal integrity analysis, RF system/antenna engineering, and wireless networking technology development. At Molex, his focus is on high-speed-interconnect signal integrity engineering and high-speed-interconnect EMC/EMI. He received his PhD in the area of computational electromagnetics from the University of Maryland, College Park. He also received his entrepreneurial training certificate from the Haas Business School at the University of California, Berkeley.

Bhavesh Patel is a principal system engineer at Dell Corp. He has more than 17 years of industry experience in hardware, signal integrity, and system design at various companies in the field of modems, telecom, and servers. Over the past eight years at Dell, he has worked on different blade server designs as a signal integrity and system engineer. His main focus is on backplane architecture, design, and simulations, as well as evaluation of various PHY equalizers for backplane applications. He earned a bachelor of science degree in electronics engineering in Bangalore, India.

Raghav Nallan is an electrical project engineer in the Connector Product Division at Molex Inc., where he focuses on high-speed I/O interconnects, signal integrity design, analysis, and measurement characterization. His has experience in system- connector-, and chip-level signal integrity. He received his MSEE from the University of South Carolina, Columbia.

Peerouz Amleshi is an electrical engineering director for the Connector Product Division at Molex Inc. His team's primary focus is in design and characterization of next-generation high-speed backplane components and systems. In his previous position as senior optical engineer at the Molex Fiber Optics Division, he was involved in the design and characterization of planar polymeric and dielectric optical integrated devices and interconnects. Amleshi holds 11 issued and two pending U.S. patents in the fields of optical and electrical interconnects. He received his PhD in the area of electromagnetics within the electrical engineering discipline from the University of Illinois at Chicago.

Casey Morrison is an applications engineer in the Data Path Solutions product line at Texas Instruments. His primary role at TI for the past five years has been architectural definition, system simulation, and test of high-speed SerDes and signal conditioning products, including advanced retimers at 25+ Gbps. His industry experience is in the area of high-speed serial communications and signal integrity spanning numerous interface standards, including Ethernet, Fibre Channel, SAS/SATA, PCI-Express, SRIO, and CPR. He received his master of science degree in electrical engineering from the University of Florida.

Jun Fan (S'97?M'00?SM'06)joined the Missouri University of Science and Technology (formerly the University of Missouri-Rolla) in July 2007 and currently is an assistant professor with the Missouri S&T EMC Laboratory. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction, differential signaling, and cable/connector designs. Fan received his bachelor and master of science degrees in electrical engineering from Tsinghua University, Beijing, in 1994 and 1997, respectively, and a PhD in electrical engineering from the University of Missouri-Rolla in 2000. From 2000 to 2007, he worked for NCR Corp. in San Diego as a consultant engineer. He served as the chair of the IEEE EMC Society TC-9 Computational Electromagnetics Committee from 2006 to 2008, and was a distinguished lecturer of the IEEE EMC Society in 2007 and 2008. He currently serves as the vice chair of the Technical Advisory Committee of the IEEE EMC Society. Fan received an IEEE EMC Society Technical Achievement Award in August 2009.

Jingook Kim joined the Ulsan National Institute of Science and Technology (UNIST; Ulsan, south Korea), where he is currently an assistant professor, in July 2011. His current research interests include 3D-IC, IC EMC, high-speed analog circuits design, RF interference, and wireless power transfer. Kim received his bachelor's, master's, and doctoral degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejon, South Korea) in 2000, 2002, and 2006, respectively. From 2006 to 2008, he was a senior engineer with the DRAM design team at the Memory Division of Samsung Electronics. From 2009 to 2011, he worked for the EMC Laboratory at the Missouri University of Science and Technolog as a postdoc fellow. He has authored or co-authored more than 50 technical papers published in refereed journals and conference proceedings. He received the Best PaperAaward from the IEEE International EMC Symposium in 2010.

Dongil Shin received a bachelor of science degree in electrical engineering from the Kumoh National Institute of Technology, South Korea, in 2012. He is currently pursuing a master's degree at the Ulsan National Institute of Science and Technology (UNIST; Ulsan, South Korea).

Junho Lee joined the Advanced Design Team of SK Hynix Semiconductor in 2006 and as a senior engineer has been responsible for the power delivery network design and EMI of DRAM chips. Lee received a bachelor of science degree in radio science and communication engineering from Hong-ik University, Seoul, in 1998, and a master of science and doctoral degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Taejon, Sourth Korea) in 2001 and 2006, respectively.

Chulsoon Hwang is a senior engineer at Samsung Electronics, Suwon,South Korea. His research interests include power and signal integrity in ICs, packages, and printed-circuit boards; electrical modeling of the IC/package/PCB system; silicon IC design; and noise immunity. Hwang received his bachelor's, master's and doctoral degrees in electrical engineering at the Korea Advanced Institute of Science and Technology (KAIST; Daejeon, South Korea) in 2007, 2009, and 2012, respectively.

Sunki Cho is a Research Engineer at SK hynix with over 5 years in the industry. He is engaged in the design and analysis of on-chip power distribution networks and high speed system simulations for signal integrity.

Eric Bogatin, signal integrity evangelist with Bogatin Enterprises, teaches advanced signal integrity classes worldwide. He received his bachelor of science degree in physics from the Massachusetts Institute of Technology in 1976 and his master's and doctoral degrees in physics from the University of Arizona in Tucson in 1980. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices

Lambert (Bert) Simonovich graduated in 1976 from Mohawk College of Applied Arts and Technology (Hamilton, Ontario) as an electronics engineering technologist. Over a 32-year career, working at Bell Northern Research/Nortel, in Ottawa, he helped pioneer the use of several advanced technologies in products. He has held a variety of engineering, research, and development positions, eventually specializing in high-speed signal integrity and backplane architectures. After leaving Nortel in 2009, he founded Lamsim Enterprises, where he continues to provide innovative signal integrity and backplane solutions as a consultant. With three patent applications and two patent grants to his name, he has also authored and coauthored several publications. His current research interests include high-speed signal integrity, modeling, and characterization of high-speed serial link architectures.

Michael Steinberger, lead architect at SiSoft Inc., has more than 30 years' experience in the design and analysis of very high-speed electronic circuits. He is currently responsible for the architecture of SiSoft's Quantum Channel Designer tool for high-speed serial channel analysis. He started his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high-speed digital backplanes used throughout Lucent's transmission product line. Before joining SiSoft, Steinberger led a group at Cray Inc., performing SerDes design, high-speed channel analysis, PCB design, and custom RAM design. He holds a PhD from the University of Southern California and has been awarded 14 patents.

Paul Wildes is a consulting engineer with SiSoft Inc. where his work focuses on signal integrity in high-end communications and networking platforms. He spent more than twenty years designing circuits and channels at Cray Inc. Mr. Wildes received the BS and MS degrees in Electrical Engineering from the University of Wisconsin, and has been awarded 2 U.S. patents. Previously he developed semi-custom IC chips at Bell Labs, and did Unix kernel development at Astronautics Corporation in Madison, Wisconsin.

Anders Ekholm, a signal integrity and timing analysis expert for Ericsson AB, started his university education in physics at Umea University, Sweden, in 1981 and received his MSc from Stockholm University in 1985. He was involved in postgraduate research at Stockholm University from 1985 to 1989 in system design. Ekholm joined Ericsson R&D in 1985, working on power integrity and EMI/EMC. He has more than 20 years' experience in the simulation and modeling of PI, SI, and EMI effects in digital systems.

Nicke Svee, hardware designer for Ericsson AB, joined Ericsson R&D in 1999 to work on high-speed serial channels, precision phase-locked loops, system level-noise budgeting, signal integrity, and timing simulation. He is currently responsible for the performance analysis of combined electrical and optical high-speed serial channels. Before joining Ericsson, Svee worked for Siemens on medical equipment projects ranging from dc motor controllers to embedded control systems. He received a BSc in electrical engineering from Sweden's Royal Institute of Technology in 1996.

Dr. Daniel Chow is a Principal Signal Integrity Engineer at Altera Corporation. His responsibilities include defining design, testing, and validation methodologies for signal integrity, power integrity, and jitter analysis in high-speed components. Specifically, he is responsible for developing Altera’s knowledge base on jitter-related issues. Before joining the industry, he was a research physicist with the U.S. Department of Energy. Dr. Chow received his Ph.D. from the University of California, Davis.

Shufang Tian is a member of the technical staff at Altera Corp. She is responsible for Altera's high-speed transceiver characterization. She received her master's degree from the University of Southern California.

Yanjing Ke is a senior member of the technical staff at Altera Corp. She is responsible for Altera's high-speed transceiver analog circuit design. She received her master's degree from Tsing Hua University and Florida International University.

Kaiyu Ren is a member of the technical staff at Altera Corp. She has worked on high-speed transceiver characterization for the past 13 years. Her scope of work includes transceiver jitter, PDNs, and signal integrity. She received her master's degree from the University of Toledo.

Martin Miller has been a hands-on engineer and designer at LeCroy for 35 years. He has contributed analog, digital, and software designs, and during the last 23 years, he has focused on measurement and display software capabilities for LeCroy scopes. He has 15 U.S. patents in this field. He holds bachelor's master's, and PhD degrees in particle physics from the University of Rochester.

Yin Wen is technical leader of the packaging engineering solutions and signal integrity team at IBM China's ASIC design center. His current focus includes 3D IC solutions, packaging engineering, and power integrity/signal integrity in ASICs used in high-speed network systems. He received a bachelor of science degree in electronics engineering from Huazhong Science and Technology University, and a master's degree in microelectronics from Shanghai Jiao Tong University.

Erik Breiland has been an application engineer at IBM Burlington for the last seven of his 14 years with IBM. Prior work included noise tool development, HSS package design, and SSO-model-to-hardware correlation. His current focus is on-chip power integrity, I/O noise analysis, and resonance analysis of customer ASIC Designs. He is also helping to develop the noise tool automation and support of current tools and methodology. He received his bachelor of science degree in electrical engineering from Rensselaer Polytechnic Institute in 1998 and a master of science degree in electrical engineering from the University of Vermont in 2005.

Ding Tong Hao is a staff hardware engineer at IBM China's ASIC design center. He received a bachelor of science degree in electrical engineering in 2007 and a PhD in electrical engineering in 2012 from China's Xidian University.

Liu Wei is a staff hardware engineer at IBM China. She focuses on package design, power integrity, and signal integrity in ASICs used in high-speed network systems, design automation support, and on-chip power noise analysis. She received her bachelor's and master's degrees in microelectronics from Fu Dan University.

Pang Ze Gui is staff hardware engineer at IBM China's ASIC design center. He focuses on package design and power noise analysis, supporting high-speed ASIC package solutions, design automation, on-chip power noise analysis, and high-speed SerDes interface modeling. He received his bachelor's and master's degrees in microelectronics from Xi Dian University.

Greg Edlund is a Senior Engineer at IBM where he has responsibility for electrical design verification of IBM enterprise and high-volume systems. He has also worked for Digital Equipment Corporation, Cray Research, and Supercomputer Systems. His book, “Timing Analysis and Simulation for Signal Integrity Engineers,” reflects his long-term interest in predicting and measuring operating margins. When he is not sitting in front of his workstation, he enjoys flying, biking, and creative writing.

Masashi Shimanouchi is a senior member of the technical staff at Altera Corp. His work on high-speed serial links of FPGA products includes link system and component architecture, mathematical modeling, characterization, and link jitter and BER simulation tools development, with expertise in signal processing, signal integrity and jitter area.

Dr. Li has been with Altera Corporation 2007 and currently is an Altera Fellow. He is a corporate expert and adviser, as well as CTO office principal investigator, on high-speed link technology, standard, SERDES architecture, electrical and optical signaling, silicon photonics, optical FPGA, high-speed simulation/debug/test, jitter, noise, signal and power integrity. He was the Chief Technology Officer (CTO) for Wavecrest Corporation from 2000-2007. Dr. Li is a Fellow of IEEE, and an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle. He holds a Ph.D. in physics (1991), an M.S.E (1991), in electrical and computer engineering and an M.S. in physics (1987), from the University of Alabama, Huntsville. He also holds a B.S (1985) in space physics from the University of Science and Technology of China. He was a Post Dr. and then a research scientist at the University of California, Berkeley (1991-1995).

Hsinho Wu is a principal engineer at Altera Corp., where he works on high-speed communication systems of FPGA products. His development and research interests include signal integrity, clock and data recovery, equalizations, and system modeling and simulation techniques. From 1999 to 2011, Wu was with National Semiconductor, where he developed high-speed interface products.

M.S. Mobin, a distinguished engineer at LSI Corp., earned his PhD in electrical engineering from Southern Methodist University in 1992. During his career, he has been involved with DSP1600 and DSP16000 series architecture definition, GSM system solutions, DSP embedded Viterbi algorithm hardware accelerators, convolution decoders, MLSE channel equalization, pre-amplifier linearization techniques, cable modem transceiver design, and SONET add/drop multiplexer design and definition. For the past seven years, he has been involved with SerDes architecture definition, system modeling, and simulation. He is deeply involved with channel equalization and timing recovery techniques. He holds more than 60 U.S. patents and has published various papers in IEEE Transactions in Biomedical Engineering and other conferences.

Amaresh Malipatil is a staff engineer at LSI Corp., where he is involved in developing system architectures for high-speed SerDes. His research interests include signal processing and communications over high-speed links and wireless channels, linear and nonlinear signal processing with applications in communications, and distributed signal processing over sensor networks. He received his bachelor of engineering degree in electronics and communications engineering from the National Institute of Technology, Karnataka, India, in 2001 and his MSEE from the University of Notre Dame in 2005.

Cathy Ye Liu heads up LSI Corp.'s SerDes Architecture group as distinuished engineer. Since 2002, she has been working on high-speed SerDes solutions. Previously, she developed read channel and mobile digital TV receiver solutions. She received her bachelor of science degree in electronic engineering from Tsinghua University, China, in 1995 and received her master's and doctoral degrees in electrical engineering from the University of Hawaii in 1997 and 1999, respectively. Her technical interests are signal processing and coding in high-speed SerDes.

Chintan Desai is director of engineering at LSI Corp. responsible for SerDes architecture, advanced development, and SerDes applications. He has 14 years of experience in SerDes development, ranging from 1G to 28G, in designer and management roles. Desai received a BSEE degree from Regional Engineering College, Surat, India, in 1988 and an MSEE from Oklahoma State University, Stillwater, in 1992.

Adam Healey is a distinguished engineer at LSI Corp., where he supports the development and standardization of high-speed serial interface products. During his tenure at Lucent Microelectronics, which later became Agere Systems and then LSI, he was involved in channel modeling and equalization strategies for high-speed optical and electrical links, transcoding and error correction coding subsystems, and transport networking architecture. Healey is a regular contributor to the development of industry standards through his work in the IEEE 802.3 Ethernet Working Group and INCITS T11.2 Fibre Channel Physical Variants Task Group. He was chairman of the IEEE P802.3ap Task Force chartered to develop the standard for Ethernet operation over electrical backplanes at speeds of 1 and 10 Gbps. He is currently secretary of the IEEE 802.3 Ethernet Working Group and chief editor for the IEEE P802.3bj 100 Gb/s Ethernet over Backplane and Copper Cable Task Force. He received bachelor of science and master of science degrees in electrical engineering from the University of New Hampshire in 1995 and 2000, respectively.

Pervez M. Aziz is an LSI Corp. distinguished engineer. In 2003, he joined the SerDes architecture group, where he works on equalization and clock/data recovery architecture development and analysis for high-speed, multi-gigabit SerDes channels. His interests also include bit-cycle-accurate functional verification of digital signal processing circuits and modeling of analog circuits. He has published six book chapters, 10 journal papers, 18 conference papers, and numerous internal technical documents. He is a recipient of the Electronics Letters Premium Award. Aziz holds more than two dozen U.S. patents. He received his bachelor's, master's, and doctoral degrees from the University of Pennsylvania in 1990, 1991, and 1996, respectively.

Pervez M. Aziz is an LSI Corp. distinguished engineer. In 2003, he joined the SerDes architecture group, where he works on equalization and clock/data recovery architecture development and analysis for high-speed, multi-gigabit SerDes channels. His interests also include bit-cycle-accurate functional verification of digital signal processing circuits and modeling of analog circuits. He has published six book chapters, 10 journal papers, 18 conference papers, and numerous internal technical documents. He is a recipient of the Electronics Letters Premium Award. Aziz holds more than two dozen U.S. patents. He received his bachelor's, master's, and doctoral degrees from the University of Pennsylvania in 1990, 1991, and 1996, respectively.

Cathy Ye Liu heads up LSI Corp.'s SerDes Architecture group as distinuished engineer. Since 2002, she has been working on high-speed SerDes solutions. Previously, she developed read channel and mobile digital TV receiver solutions. She received her bachelor of science degree in electronic engineering from Tsinghua University, China, in 1995 and received her master's and doctoral degrees in electrical engineering from the University of Hawaii in 1997 and 1999, respectively. Her technical interests are signal processing and coding in high-speed SerDes.

Adam Healey is a distinguished engineer at LSI Corp., where he supports the development and standardization of high-speed serial interface products. During his tenure at Lucent Microelectronics, which later became Agere Systems and then LSI, he was involved in channel modeling and equalization strategies for high-speed optical and electrical links, transcoding and error correction coding subsystems, and transport networking architecture. Healey is a regular contributor to the development of industry standards through his work in the IEEE 802.3 Ethernet Working Group and INCITS T11.2 Fibre Channel Physical Variants Task Group. He was chairman of the IEEE P802.3ap Task Force chartered to develop the standard for Ethernet operation over electrical backplanes at speeds of 1 and 10 Gbps. He is currently secretary of the IEEE 802.3 Ethernet Working Group and chief editor for the IEEE P802.3bj 100 Gb/s Ethernet over Backplane and Copper Cable Task Force. He received bachelor of science and master of science degrees in electrical engineering from the University of New Hampshire in 1995 and 2000, respectively.

Ketan Shringapure (S'10) received his B.E. degree in electronics and telecommunication at Mumbai University in 2007, and his master of science degree in electrical engineering at Missouri University of Science and Technology in 2010. He is currently pursuing his PhD at Missouri S&T. He has been a research assistant at the Missouri S&T EMC Laboratory since 2008. His research interests include power bus modeling and analysis for PCBs and ICs, and signal integrity for high-speed links.

Siming Pan (S'09) is a hardware engineer with Cisco Systems' Advanced Manufacturing Technology Center. His research interests include high-speed digital designs, signal integrity analysis for printed-circuit boards, dc power bus systems, and system-level power distribution networks. Pan received his bachelor of science degree in electrical engineering from Tsinghua University, Beijing, in 2008 and his master of science degree in electrical engineering from the Missouri University of Science and Technology (formerly the University of Missouri-Rolla) in 2010. He received the the IEEE EMC Society President's Memorial Award in 2009.

Brice Achkir is a distinguished engineer at Cisco Inc., where he focuses on high-speed design, signal/power integrity, and design/architecture of high-speed systems. His research interests include high-speed digital and mixed-signal designs, active and adaptive optics, and networking. His past experience includes research and development in optics design, microwave, and RF areas. Achkir received bachelor's, master's and doctoral degrees in applied physics, physics, and computer science.

Bruce Archambeault (M'85?SM'99?F'05) is an IBM distinguished engineer in Research Triangle Park, NC. Archambeault has authored or co-authored a number of papers in computational electromagnetics, mostly applied to real-world EMC applications. He is a current member of the board of directors for the IEEE EMC Society and a past member of the board of directors for the Applied Computational Electromagnetics Society (ACES). He has served as a past IEEE/EMCS distinguished lecturer and associate editor for the IEEE Transactions on Electromagnetic Compatibility. Archambeault received his bachelor of science degree in electrical engineering from the University of New Hampshire in 1977, his master's degree in electrical engineering from Northeastern University in 1981, and his PhD from the University of New Hampshire in 1997.

Jun Fan (S'97?M'00?SM'06)joined the Missouri University of Science and Technology (formerly the University of Missouri-Rolla) in July 2007 and currently is an assistant professor with the Missouri S&T EMC Laboratory. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction, differential signaling, and cable/connector designs. Fan received his bachelor and master of science degrees in electrical engineering from Tsinghua University, Beijing, in 1994 and 1997, respectively, and a PhD in electrical engineering from the University of Missouri-Rolla in 2000. From 2000 to 2007, he worked for NCR Corp. in San Diego as a consultant engineer. He served as the chair of the IEEE EMC Society TC-9 Computational Electromagnetics Committee from 2006 to 2008, and was a distinguished lecturer of the IEEE EMC Society in 2007 and 2008. He currently serves as the vice chair of the Technical Advisory Committee of the IEEE EMC Society. Fan received an IEEE EMC Society Technical Achievement Award in August 2009.

James L. Drewniak (F'09) received his bachelor's , master's, and PhD degrees in electrical engineering from the University of Illinois, Urbana-Champaign, in 1985, 1987, and 1991, respectively. He is currently with Electromagnetic Compatibility (EMC) Laboratory in the Electrical Engineering Department of the Missouri University of Science and Technology. His research and teaching interests include electromagnetic compatibility in high-speed digital and mixed-signal designs, signal and power integrity, electronic packaging, electromagnetic compatibility in power-electronics-based systems, electronics, and antenna design. He is an associate edirtor for the IEEE Transactions on EMC.

Jingook Kim joined the Ulsan National Institute of Science and Technology (UNIST; Ulsan, south Korea), where he is currently an assistant professor, in July 2011. His current research interests include 3D-IC, IC EMC, high-speed analog circuits design, RF interference, and wireless power transfer. Kim received his bachelor's, master's, and doctoral degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST; Daejon, South Korea) in 2000, 2002, and 2006, respectively. From 2006 to 2008, he was a senior engineer with the DRAM design team at the Memory Division of Samsung Electronics. From 2009 to 2011, he worked for the EMC Laboratory at the Missouri University of Science and Technolog as a postdoc fellow. He has authored or co-authored more than 50 technical papers published in refereed journals and conference proceedings. He received the Best PaperAaward from the IEEE International EMC Symposium in 2010.

Arul Kandasamy manages the power delivery team in the Netbook and Tablet Group at Intel Corp. He has 20 years of experience in embedded system design. In the past eight years at Intel, he led many signal integrity and power integrity efforts for the client, desktop, and netbook team.

David G. Figueroa manages the server power integrity team at Intel Corp. He has spent the past 16 years in Intel and has worked on several electrical modeling and interconnect characterization challenges. He holds more than 10 patents.

Jiangqi He is an analog engineer leading the server power integrity design activities at Intel Corp. He has a PhD in electrical engineering and holds more than 10 patents.

Richard Sjiariel studied EE at the University of Wuppertal and received his M.Sc. degree in 2006. The same year he joined CST as an Application Engineer, where his main area of applications includes Signal/Power Integrity, EMC/EMI Simulation and also other high frequency applications.

Joachim Held is an EMC design engineer at Siemens AG, where he currently focuses on PI simulation in research and development for motion-control systems. He graduated in 1986 with an electrical engineering degree from the Technical University of Erlangen, Germany. He Joined Siemens in 1996, delivering EMC design-support with measurement and simulation. He has contributed innovations in the principle of inductive current-dividing for supply systems and a special measurement method for VLSI supply currents.

Bipin Dhavale is a senior signal and power integrity engineer at Altera Corp., where his responsibilities include signal integrity and power delivery network analysis and characterization. He was most recently a signal integrity engineer in the pre-development team at Qimonda AG, where he was responsible for channel design and simulation of multi-slot DDR2/DDR3 systems, particularly feasibility simulations of a twin-buffer load reduced DIMM for high-density memory applications. He received his master's degree in electrical engineering from Virginia Polytechnic Institute and State University.

June Feng is a member of the technical staff at Altera Corp., where she is is responsible for channel VT budget simulation and high-speed channel characterization. She joined Altera in 2011 and earlier worked at Amkor and Rambus. She has been involved in performing detailed analysis, modeling, design, and characterization in a variety of areas, including high-speed, low-cost PCB layout and device packaging. Her interests include high-speed interconnects modeling, channel VT budget simulation, power delivery network modeling, and high-frequency measurements. She received her master of science degree from the University of California, Davis, and her bachelor's degree from Beijing University.

Yuri Tretiakov is a senior member of the technical staff at Altera Corp. He received his MS degree in electrical engineering from the Moscow Institute of Physics and Technology and his PhD in electrical engineering from Arizona State University, Tempe. Currently, he is working on power delivery network characterization, high-speed hardware evaluation, and the design of FPGA characterization boards. He has authored or co-authored 35 journal and conference papers. He also published a book chapter and has two U.S. patents issued.

Janani Chandrasekhar is a senior signal integrity/power integrity engineer at Altera Corporation. Her responsibilities include performing SI/PI co-simulation for GPIO interfaces, simulation and validation of on chip power supply induced jitter for high speed transceivers and ensuring system level signal integrity for high-speed transceivers and GPIOs. She received a MSECE degree and thesis from Georgia Institute of Technology. She has prior experience from NVIDIA where she worked on high speed modeling, design and characterization of different high speed interfaces.

Shishuang Sun is a manager with the signal integrity and transceiver characterization group at Altera Corp. His research interests include signal integrity in high-speed transceiver, on-chip and system-level power delivery network design and modeling, and jitter and timing impact from on-chip PDN noise. He holds a PhD in electrical engineering from the Missouri University of Science and Technology (formerly the University of Missouri-Rolla). He received DesignCon 2010 paper awards and has authored more than 20 journal and conference papers.

Dr. Mayra Sarmiento is a MTS Design Engineer at Altera Corporation. She focuses on signal integrity, power integrity, and ODC projections. Dr. Sarmiento received her BS in Electronic Engineering from the Pontifical Xavier University (Pontificia Universidad Javeriana) of Bogota, Colombia and her Ph.D. in Electrical Engineering from the University of Delaware, Newark.

Sunitha Chandra is a Member of Technical Staff at Altera focused in the area of Signal and Power Integrity. She is responsible for signal and power integrity methodologies and design guidelines for product development. Prior to her work at Altera she worked at Nvidia as a senior signal integrity engineer. She received her Masters degree in Electrical Engineering from Missouri University of Science and Technology (formerly University of Missouri-Rolla). Her interests include PDN analysis, system level channel optimization, timing analysis and closure for serial and parallel interfaces.

Dr. Daniel Chow is a Principal Signal Integrity Engineer at Altera Corporation. His responsibilities include defining design, testing, and validation methodologies for signal integrity, power integrity, and jitter analysis in high-speed components. Specifically, he is responsible for developing Altera’s knowledge base on jitter-related issues. Before joining the industry, he was a research physicist with the U.S. Department of Energy. Dr. Chow received his Ph.D. from the University of California, Davis.

Aman Aflaki is a Lead Staff Signal Integrity engineer at Altera Corporation. He is responsible for signal and power integrity modeling and high speed transceiver characterization. He holds MSEE in Electrical Engineering from Missouri University of Science and Technology, and BSEE from Isfahan University of Technology. He has published papers in IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT and DesignCon. He holds two patent in the field of signal integrity for wafer sort testing.

Weiliang Yuan is a principal engineer with Samsung Electronics' Power/Signal Integrity Enabling Group and works on off-chip power and signal integrity analysis, characterization, and chip-package-board co-design. From 2005 to 2011, he worked at United Test and Assembly Center in Singapore on IC package electrical analysis, characterization, and design for various applications as a principal engineer. From 1999 to 2005, he was a senior research engineer at the Institute of High-Performance Computing in Singapore.

Sangmin Lee leads SoC/AP platform integrity and electrical validation as a principal engineer at Samsung Electronics. He has been responsible for I/O platform enabling activities and design methodology development for high-speed memory and serial interfaces. Before Samsung, Lee worked as a senior component design engineer at Intel Corp., where he developed tests and tools for system validation of chip sets and processors.

Chanmin Jo is a senior engineer at Samsung Electronics, having joined the company in 2006. He is responsible for the development of modeling and analysis for high-speed memory interfaces. He received bachelor of science and master of science degrees in electrical engineering from Hanyang University, South Korea, in 2004 and 2006, respectively, with a focus on modeling and characterization for signal integrity of high-speed integrated circuits, IC interconnect, and IC packaging.

Seungbae Lee is with Samsung Electronics and works on electromagnetic interference/susceptibility qualification as a senior engineer in the Technology Quality and Reliability group. His current research interest is the power distribution network impedance specification. He received his bachelor's degree in electronics and communication engineering from Kwangwoon University, Seoul, in 1996 and his master's degree semiconductor systems engineering from Sungkyunkwan University, Suwon, South Korea, in 2009.

Seungbae Lee is with Samsung Electronics and works on electromagnetic interference/susceptibility qualification as a senior engineer in the Technology Quality and Reliability group. His current research interest is the power distribution network impedance specification. He received his bachelor's degree in electronics and communication engineering from Kwangwoon University, Seoul, in 1996 and his master's degree semiconductor systems engineering from Sungkyunkwan University, Suwon, South Korea, in 2009.

Suzanne L. Huh, an engineer with Intel Corp.'s SoC Signal Integrity/Power Delivery Group, completed her PhD in electrical and computer rngineering at the Georgia Institute of Technology in 2011.

Xioping A. Liu is an engineer with Intel Corp.'s SoC Signal Integrity/Power Delivery Group.

Vishram S. Pandit is currently a manager at Intel Corp. He works on developing power delivery designs for high-speed interfaces. His focus areas include high-speed system power delivery, on-chip power delivery, and signal/ power integrity co-design.

Om P. Mandhana has been a senior staff product engineer at Cadence Design Systems since July 2012. His current responsibilities include developing modeling and simulation methodology and strategies for package electrical characterizations, and design-oriented modeling and simulation analysis of microprocessor systems for noise-performance assessment-based design closures. Manhanda earlier worked at Sigrity, Freescale, and IBM. He has also worked as an assistant professor at the University of Kentucky, Lexington; as a lecturer at the University of Missouri, Columbia; and as a lecturer at Birla Institute of Technology and Science, Pilani, India. His research interest includes design-oriented power and signal integrity simulation-analysis-based high-performance microprocessor packaging systems. He has authored several journal and conference papers in the field of system-level power integrity, signal integrity, and power electronics. He received his PhD in electrical engineering from University of Missouri.

Xiaoxia Zhou ia a hardware engineer at the Cisco Systems (China) R&D Center, where he specializes in EMC simulations and EMC design. Before joining Cisco, he worked at CST as an application engineer and at Motorola as an RF engineer. He received his master of science degree radio physics from University of Electronic Science and Technology of China.

Hongmei Fan has been working at the Cisco Systems (China) R&D Center as an EMC simulation engineer since 2010. She received her B.Eng. in solid electronics from Huazhong University of Science & Technology in 1992, her M.Eng. in metallic material and annealing from the Shanghai Institute of Metallurgy in 1995, and her PhD in electrical engineering from The University of Western Australia in 2009.

Jing Li received her master of science degree in electrical engneering from Beijing Jiaotong University in China in 2008. Currently she is a co-op student in the EMC design group at Cisco Systems, San Jose, and has been a PhD student in the EMC laboratory in Missouri University of Science and Technology (MST) since 2010. Before pursuing PhD study at MST, she worked at Beijing Sony Ericsson Potevio Mobile Communications as an RF electrical verification engineer.

Kam Taunk has been an EMC compliance engineer at Cisco Systems in San Jose for more then 11 years and has been at Cisco for more than 16 years. He has more than 34 years of working experience at Fortune 500 companies, including 11 years at IBM, conducting component-level failure analysis and driving the corrective action, as well as leading a group of six engineers in the FA Lab. He received his associate degree in electronics at Mission College and completed undergraduate courses.

Alpesh U. Bhobe is a technical leader at Cisco Systems in San Jose, where he works on EMC design. He received his BE degree in electrical and telecommunication engineering from the University of Bombay and receive a PhD in electrical engineering from the University of Colorado at Boulder in 2003. He was a post-doc at the National Institute of Standards and Technology in Boulder. While at the University of Colorado and at NIST, his research interests included the development of FDTD and FEM code for EM and microwave applications.

Jinghan Yu is an engineering manager at the Cisco Systems (China) R&D Center, where he leads a group of EMC and power design engineers as well as library and tool support engineers. Before joining Cisco, he was an EMC engineer at Andiamo Inc. in San Jose. He received his bachelor of science degree in control science and engineering from Zhejiang University, China, in 1998 and his master's degree in electrical engineering from Louisiana State University in 2001.

Philippe Sochoux joined Cisco Systems in 1998 and worked as an EMC and a signal integrity engineer on the Cat6K family of switches. Since 2001, he has managed CAD and signal integrity teams and is currently responsible for the EMC design and test of Cisco Systems' product lines. Before joining Cisco, he was a regulatory engineer at U.S. Robotics/3COM in Chicago. He received his bachelor of science and master of science degrees in electrical engineering from Marquette University, in 1990 and in 1994, respectively.

Bruce Archambeault (M'85?SM'99?F'05) is an IBM distinguished engineer in Research Triangle Park, NC. Archambeault has authored or co-authored a number of papers in computational electromagnetics, mostly applied to real-world EMC applications. He is a current member of the board of directors for the IEEE EMC Society and a past member of the board of directors for the Applied Computational Electromagnetics Society (ACES). He has served as a past IEEE/EMCS distinguished lecturer and associate editor for the IEEE Transactions on Electromagnetic Compatibility. Archambeault received his bachelor of science degree in electrical engineering from the University of New Hampshire in 1977, his master's degree in electrical engineering from Northeastern University in 1981, and his PhD from the University of New Hampshire in 1997.

Samuel Connor is a Senior Technical Staff Member at IBM and is responsible for the development of EMC and SI analysis tools/applications. Mr. Connor's current work activities and research interests also include electromagnetic modeling and simulation in support of power distribution and link path design for printed circuit boards. He has co-authored numerous papers in computational electromagnetics, mostly applied to decoupling and high-speed signaling issues in PCB designs. He is a Senior Member of the IEEE and is currently the chairman of the Eastern NC chapter and the TC-9 subcommittee of the IEEE EMC Society.

Yin-Chen Lu is the senior manager of customereEngineering at SiTime Cor. Before SiTime, he held engineering, product management. and marketing positions at a number of technology companies. Lu's technical expertise includes RF, optical electronics, and communication system design and testing. He received his BE from Southeast University in Nanjing, China, and his MSEE and PhD from the University of New Mexico, Albuquerque.

Chris Di Minico is president of MC Communications, a telecommunications consulting firm. He has more than 30 years of experience in the telecom industry and plays an active role in the development of a number of industry standards. Di Minico is an active participant and technical contributor to the 802.3ba standard, participating as editor of Clause 92 and Annex 92A, Type 100GBASE-CR4. He was the co-chair for TIA/EIA?942, "Telecommunications Infrastructure Standard for Data Centers," and is the IEEE 802.3 liaison to TIA-TR42.

Mike Sapozhnikov is a technical leader at Cisco Systems, where he works on 3D modeling, channel design, material extractions, manufacturing tolerances, and package and system development. He received his bachelor of science degree in electrical engineering from San Jose State University. He has 15 years of experience with SI/PI, system design and Ethernet transceiver technology.

Mike Resso is a signal integrity application scientist in the Component Test Division of Agilent Technologies and has more than 25 years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high-speed digital interconnects using time-domain reflectometry and vector network analysis. He has authored more than 30 professional publications, including a book on signal integrity. Resso has been awarded one U.S. patent and has twice received the Agilent Spark of Insight Award for his contribution to the company. He received a bachelor of science degree in electrical and computer engineering from the University of California.

Henry Zeng was born in 1981. He received the Bachelor and Master degrees in Mechanical and Electronic Engineering from Xidian University, Xi’an, China, in 2007. From March 2004 to March 2007, he attended a research funded by Chinese government, which studied the coupling among forces/stress/ vibration, heat and electromagnetic field in electronic devices. He was mainly responsible for the electromagnetic field. In April 2007, he joined NVIDIA. He is focusing on EMC/RF design, analysis and certification and antenna design and analysis.

Charlie Shu is currently an Engineering Manager at NVIDIA Crop. He joined NVIDIA as a senior engineer in 2001. Previously, he had held engineer, technical staff, and senior technical staff positions in several Silicon Valley companies, including Apple Inc. and Sun Microsystems since 1987. He holds a BSEE degree from Beijing University of Technology and a MSCS degree from Ohio University.

Charles Jackson is an SI/EMC Compliance Engineering Manager at NVIDIA Corporation. He has over 30 years’ experience in the EMC field working in the areas of medical devices, commercial/military avionics, consumer electronics, and passive components. He received his BSEE from the University of Minnesota.

Jan Van Hese received his engineering degree in Electronics (specialty High-Frequency Modeling) from the University of Gent, Belgium in 1988 and a PhD. degree from the same University on EM modeling and simulation in 1993. After finishing his PhD in 1993, he started working for the Alphabit company located in Gent, Belgium as a software developer. This company was a spin-off of from Imec working on the development of the planar EM simulator Momentum which was commercialized by Hewlett-Packard. In 1994 the Alphabit company was acquired by Hewlett-Packard. In terms of development work, Jan Van Hese contributed to the Green function module and the farfield calculation module within the Momentum product. In 1998, he became an R&D project manager responsible for the Momentum product as a whole within the EEsof division. In 1999 EEsof became part of Agilent Technologies after the creation of the Agilent spin-off from HP. Currently Jan Van Hese is responsible for the development the 3D EM products within Agilent EEsof,. Jan Van Hese is author of one patent.

Francesco de Paulis is a research associate at the University of L'Aquila, Italy. He received the laurea, specialistic (summa cum laude) and doctoral degrees in electronic engineering from the University of L'Aquila in 2003, 2006 and 2011, respectively. He also received a master's degree in electrical engineering from the Missouri University of Science and Technology, in 2008. His main research interests are in developing fast and efficient analysis tools for SI/PI and design of high-speed signals on PCBs, composite material analysis and characterization, RF interference in mixed-signal system, and EMI investigations on PCBs.

Muhammet Hilmi Nisanci is a PhD student at the University of L'Aquila, Italy.

Antonio Orlandi has been with the Department of Electrical Engineering of the University of L'Aquila since 1990 and currently is a full professor and chair of the university's EMC Laboratory. Author of more than 200 technical papers, he has published in the field of electromagnetic compatibility in lightning protection systems and power drive systems. Current research interests are numerical methods and modeling techniques to approach signal/power integrity and EMC/EMI issues in high-speed digital systems. Orlandi received the IEEE Transactions on Electromagnetic Compatibility Best Paper Award in 1997; the IEEE EMC Society Technical Achievement Award in 2003; the IBM Shared University Research Award in 2004, 2005 and 2006; the CST University Award in 2004; and the IEEE International Symposium on EMC Best Paper Award in 2009. He is member of the Education and TC-9 Computational Electromagnetics Committees and chairman of the TC-10 Signal Integrity Committee of the IEEE EMC Society. From 1996 to 2000, he was associate editor of the IEEE Transactions on Electromagnetic Compatibility; and from 2001 to 2006, he was associate editor of the IEEE Transactions on Mobile Computing. He received a laurea degree in electrical engineering from the Sapienza University of Rome in 1988 and was with the university's Department of Electrical Engineering from 1988 to 1990.

Xiaoxiong (Kevin) Gu is a research staff member at IBM's Thomas J. Watson Research Center. His research interests include characterization of high-speed interconnect and microelectronic packaging, signal integrity, and computational electromagnetics. He received his bachelor of science degree from Tsinghua University, Beijing, in 2000; master's degree from the University of Missouri-Rolla in 2002; and PhD from the University of Washington, Seattle, in 2006, all in electrical engineering.

Renato Rimolo-Donadio joined the IBM T.J. Watson Research Center in 2012 as a postdoctoral researcher. From 2006 to 2011, he was with the Institute of Electromagnetic Theory at the Technical University of Hamburg-Harburg, Germany. His current research interests include system-level modeling and optimization of interconnects, and analysis of signal and power integrity problems at the PCB and package levels. Rimolo-Donadio received his bachelor's and license degrees in electrical engineering from the Technical University of Costa Rica, Cartago, in 1999 and 2004, respectively, and his master's degree with distinction in microelectronics and microsystems and doctoral degree summa cum laude in electrical engineering from the Technical University of Hamburg-Harburg in 2006 and 2010, respectively.

Christian W. Baks joined the IBM T.J. Watson Research Center as a staff engineer in 2001. Baks is involved in high-speed optoelectronic package and backplane interconnect design, specializing in signal integrity issues. He received a bachelor of science degree in applied physics from Fontys College of Technology, Eindhoven, Netherlands, in 2000 and a master of science degree in physics from the State University of New York at Albany in 2001.

Samuel Connor is a Senior Technical Staff Member at IBM and is responsible for the development of EMC and SI analysis tools/applications. Mr. Connor's current work activities and research interests also include electromagnetic modeling and simulation in support of power distribution and link path design for printed circuit boards. He has co-authored numerous papers in computational electromagnetics, mostly applied to decoupling and high-speed signaling issues in PCB designs. He is a Senior Member of the IEEE and is currently the chairman of the Eastern NC chapter and the TC-9 subcommittee of the IEEE EMC Society.

Bruce Archambeault (M'85?SM'99?F'05) is an IBM distinguished engineer in Research Triangle Park, NC. Archambeault has authored or co-authored a number of papers in computational electromagnetics, mostly applied to real-world EMC applications. He is a current member of the board of directors for the IEEE EMC Society and a past member of the board of directors for the Applied Computational Electromagnetics Society (ACES). He has served as a past IEEE/EMCS distinguished lecturer and associate editor for the IEEE Transactions on Electromagnetic Compatibility. Archambeault received his bachelor of science degree in electrical engineering from the University of New Hampshire in 1977, his master's degree in electrical engineering from Northeastern University in 1981, and his PhD from the University of New Hampshire in 1997.

Young H. Kwark received his BSEE from the Massachusetts Institute of Technology and his MSEE/PhD from Stanford University. His work experience as a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, includes circuit design for optical links and wireless applications. He is currently involved in package characterization for high performance computing platforms. Dr. Kwark is the recipient/co-recipient of DesignCon Paper Awards in 2005, 2006, 2008 and 2010.

Gregory Fitzgerald is a Sr. Signal Integrity Engineer with Molex’s High Performance Cable Assemblies Business Unit, working in the Boston area. Greg’s responsibilities include simulation and modeling of cable assemblies and new product development for gigabit cable applications. Greg’s past experience and interests include high speed design, computer simulation and technical sales.

Munawar Ahmad is a Principal Engineer and Molex Fellow with Molex’s High Performance Cable Business Unit. He has designed and developed test methodologies for high performance cable assemblies for multi-gigabit application. Munawar was an electrical engineering professor before joining Molex in 1995. He enjoys teaching short courses on signal integrity and high-speed testing, and mentoring new employees and interns.

Mark Bugg is a Project Engineer with Molex’s High Performance Cable Assemblies Business Unit and has been instrumental in the design and test of 4X25Gbps copper cable assemblies. Mark has been involved in copper cable high-speed standards development and currently is involved with the IEEE 802.3bj 100Gbps Backplane and Copper Cable Task Force.

Michael Rost is a Project Engineer with Molex’s High Performance Cable Assembly Business Unit. His current responsibilities include the design and simulation of 25 Gbps+ backplane copper cable assemblies. Michael’s past responsibilities have included design, simulation, production, and test and measurement of multi-gigabit copper cable assemblies. He has been active in several industry groups such as the IBTA, PCI-SIG, SFF, and T10.

Jose Moreira is a staff engineer on the test cell innovations team of the SOC bussiness unit at Advantest in Böblingen, Germany. He focuses on the challenges of testing high-speed digital devices especially in the area of test fixture design, signal integrity, jitter testing and focus calibration. He joined Agilent Technologies in 2001 (later Verigy and in 2011 acquired by Advantest) and holds a Master of Science degree in Electrical and Computer Engineering from the Instituto Superior Técnico of the Technical University of Lisbon, Portugal. He is a senior member of the IEEE and co-author of the book “A Engineers Guide to Automated Testing of High-Speed Digital Interfaces”.

Marc Möessinger has an Engineering Degree from University of Applied Science in Ulm, Germany and MSc from Brunel University of West London, UK. He started his career with Hewlett-Packard in 1997 as Hardware Design Engineer. He developed Firmware, Hardware and ASICs for Automated Test Equipment for HP, Agilent Technologies, and Verigy. Since 2003 he is managing projects and leading the High-Speed Memory Hardware R&D team responsible for Test-Cell developments.

Masayuki Takahashi is a professional with the Design Department of the Advanced DRAM Design Group at Elpida Atsugi, Japan. He has an electrical engineering degree from Kogakuin University and joined Elpida in 2002.

Tom Bresnan is the marketing manager with R&D Circuits of South Plainfield, NJ. His more than 30 years of printed circuitmanufacturing experience includes positions in various engineering and management roles for some of the world’s largest manufacturers of complex printed circuit boards. He is a distinguished lifetime member of the IPC (a US based, global trade organization representing the printed circuit industry) technical activities executive committee, and has presented and published numerous technical articles for the industry on MCM-L’s, board fabrication and advanced plating capabilities. He is presently studying at Seton Hall University in NJ for an advanced degree in Theology.

Dr. Daniel Chow is a Principal Signal Integrity Engineer at Altera Corporation. His responsibilities include defining design, testing, and validation methodologies for signal integrity, power integrity, and jitter analysis in high-speed components. Specifically, he is responsible for developing Altera’s knowledge base on jitter-related issues. Before joining the industry, he was a research physicist with the U.S. Department of Energy. Dr. Chow received his Ph.D. from the University of California, Davis.

Yujeong Shim is a senior signal integrity engineer at Altera Corporation. Her responsibility includes jitter modeling on high speed serial links and power distribution network design on system level. She received the B.S, the M.S and the Ph.D degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2005, 2007, and 2011 respectively. She worked as a visiting researcher at Silicon Image, Inc., Sunnyvale, California, US in 2008. In 2009, she was involved as an internship in RF and mm-wave modeling and characterization team at IMEC, Leuven, Belgium. She is an author/a co-author of 32 IEEE SCI journal /conference, and received the best paper awards at the 2007 Electromagnetic Compatibility (EMC) Compo, Torino, Italy and the DesignCon 2011 event.

Shishuang Sun is a manager with the signal integrity and transceiver characterization group at Altera Corp. His research interests include signal integrity in high-speed transceiver, on-chip and system-level power delivery network design and modeling, and jitter and timing impact from on-chip PDN noise. He holds a PhD in electrical engineering from the Missouri University of Science and Technology (formerly the University of Missouri-Rolla). He received DesignCon 2010 paper awards and has authored more than 20 journal and conference papers.

Jack Carrel is an applications engineer at Xilinx. He has more than 25 years of experience in product development and design in the fields of instrumentation, test and measurement, and telecommunications. His background includes development of electro-optic modules, multi-gigabit transceiver boards, and high-speed and high-resolution data acquisition systems for government and commercial applications. Most recently, he has been involved in product design using multi-gigabit transceivers with a specific focus on PCB design issues. He has published in several professional publications. Carrel received his bachelor of science degree in electrical engineering from the University of Oklahoma.

Heidi Barnes is a senior application engineer for high-speed digital applications in the EEsof EDA Group of Agilent Technologies. Her past experience includes more than six years in signal integrity for ATE test fixtures for Verigy, an Advantest Group, and six years in RF/microwave microcircuit packaging for Agilent Technologies. She rejoined Agilent Technologies in April. Barnes holds a bachelor of science degree in electrical engineering from the California Institute of Technology.

Mike Resso is a signal integrity application scientist in the Component Test Division of Agilent Technologies and has more than 25 years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high-speed digital interconnects using time-domain reflectometry and vector network analysis. He has authored more than 30 professional publications, including a book on signal integrity. Resso has been awarded one U.S. patent and has twice received the Agilent Spark of Insight Award for his contribution to the company. He received a bachelor of science degree in electrical and computer engineering from the University of California.

Rob Sleigh is a Product Marketing Engineer for sampling scopes in Agilent Technologies’ Oscilloscope Products Division. He is responsible for product development for the division’s high-speed electrical and optical digital communications analyzer and jitter test products. Rob’s experience at Agilent Technologies/Hewlett-Packard includes 5 years in technical support, and over 8 years in sales and technical marketing. Prior to working at Agilent Technologies/HP, Rob worked for 10 years at Westel Telecommunications in Vancouver, British Columbia, Canada, designing microwave and optical telecommunication networks. Rob earned his B.S.E.E. degree from the University of Victoria.

Hoss Hakimi is a principal engineer at Xilinx Inc. He has more than 20 years of experience, specializing in high-level behavioral modeling and top-down design methodology in ASIC/FPGA design, synthesis, substrate design, 3D interconnect parasitic extraction, high-speed signal integrity, and PCB power integrity and simulation. He holds an electrical engineering degree from San Jose State University and has completed MS courses in the EE department at the University of California, Berkeley.

Peter Pupalaikis has worked at LeCroy (now LeCroy Teledyne) for 17 years and currently manages IC development and intellectual property as vice president of technology development. Before LeCroy, he served in the United States of America Army and as a consultant in embedded-systems design. Pupalaikis has numerous patents in the area of measurement-instrument design and is a member of Tau Beta Pi, Eta Kappa Nu and the IEEE signal processing, instrumentation, and microwave societies. He received a bachelor of science degree in electrical engineering from Rutgers University in 1988.

Kaviyesh Doshi received his PhD in electrical engineering from the University of California, Santa Barbara in June 2008 and joined LeCroy in August 2008 as a research and development engineer. At LeCroy, he has been involved in design and development of SPARQ, a TDR-based instrument for measuring S-parameters. He has filed patents in the area of de-embedding and signal processing for a time-domain network analyzer.

Sarah Paydavosi is a hardware engineer at Oracle Corp. Her current work focuses on signal integrity modeling, analysis, and validation in Oracle's MicroElectronics ASIC and SoC IP group. She received her PhD in electrical engineering from Massachusetts Institute of Technology.

Laura Kocubinski is a hardware engineer at Oracle Corp. Currently, she works on signal integrity within Oracle's SPARC T-Series server division. She received her BSEE, with a technical concentration in communications and information processing, from Rensselaer Polytechnic Institute in 2012.

Gustavo J. Blando is a Principle Hardware Engineer with over ten years of experience in the industry. Currently at Oracle Corporation, he is responsible for the development of new processes and methodologies in the areas of broadband measurement, high speed modeling and system simulations. He received his M.S. from Northeastern University.

Istvan Novak is a senior principal engineer at Oracle Corp. Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of power-distribution networks and packages for midrange servers. He creates simulation models and develops measurement techniques for power distribution. Novak has more than 20 years of experience with high-speed digital, RF, and analog circuit and system design. He has been made an IEEE fellow for his contributions to signal integrity and RF measurement and simulation methodologies.

Christian W. Baks joined the IBM T.J. Watson Research Center as a staff engineer in 2001. Baks is involved in high-speed optoelectronic package and backplane interconnect design, specializing in signal integrity issues. He received a bachelor of science degree in applied physics from Fontys College of Technology, Eindhoven, Netherlands, in 2000 and a master of science degree in physics from the State University of New York at Albany in 2001.

Renato Rimolo-Donadio joined the IBM T.J. Watson Research Center in 2012 as a postdoctoral researcher. From 2006 to 2011, he was with the Institute of Electromagnetic Theory at the Technical University of Hamburg-Harburg, Germany. His current research interests include system-level modeling and optimization of interconnects, and analysis of signal and power integrity problems at the PCB and package levels. Rimolo-Donadio received his bachelor's and license degrees in electrical engineering from the Technical University of Costa Rica, Cartago, in 1999 and 2004, respectively, and his master's degree with distinction in microelectronics and microsystems and doctoral degree summa cum laude in electrical engineering from the Technical University of Hamburg-Harburg in 2006 and 2010, respectively.

Young H. Kwark received his BSEE from the Massachusetts Institute of Technology and his MSEE/PhD from Stanford University. His work experience as a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, includes circuit design for optical links and wireless applications. He is currently involved in package characterization for high performance computing platforms. Dr. Kwark is the recipient/co-recipient of DesignCon Paper Awards in 2005, 2006, 2008 and 2010.

Fuad E. Doany is a research staff member at IBM's Thomas J. Watson Research Center, where he has focused on high-speed optical link and systems design and optoelectronics packaging. He has worked on laser spectroscopy, applied optics, projection displays, and laser material processing for electronic packaging. Doany received a PhD in physical chemistry from the University of Pennsylvania in 1984 and was a postdoctoral fellow with the California Institute of Technology from 1984 to 1985. He is an author or co-author of many technical papers and holds more than 40 U.S. patents. He is a member of the Optical Society of America.

Xiaoxiong (Kevin) Gu is a research staff member at IBM's Thomas J. Watson Research Center. His research interests include characterization of high-speed interconnect and microelectronic packaging, signal integrity, and computational electromagnetics. He received his bachelor of science degree from Tsinghua University, Beijing, in 2000; master's degree from the University of Missouri-Rolla in 2002; and PhD from the University of Washington, Seattle, in 2006, all in electrical engineering.

Daniel M. Kuchta is a research staff member in the Communication Technology Department at IBM's Thomas J. Watson Research Center, where he has worked on high-speed VCSEL characterization, multimode fiber links, and parallel fiber-optic link research. Kuchta received bachelor of science, master of science and doctoral degrees in electrical engineering and computer science from the University of California, Berkeley in 1986, 1988, and 1992, respectively. He is an author or co-author of 10 patents and more than 50 technical papers.

Benjamin G. Lee is a postdoctoral researcher with IBM's Thomas J. Watson Research Center. His research interests include silicon photonic devices, integrated optical switches and networks for high-performance computing systems, and highly parallel multimode transceivers. He received a bachelor of science degree from Oklahoma State University, Stillwater, in 2004 and master's and doctoral degrees from Columbia University in 2006 and 2009, respectively, all in electrical engineering. Lee is a member of the IEEE Photonics Society and the Optical Society of America.

Alexander V. Rylyakov joined IBM's Thomas J. Watson Research Center in 1999 as a research staff member. His main area of interest is digital phase research. Rylyakov received an MS degree in physics from Moscow Institute of Physics and Technology in 1989 and a PhD in physics from the State University of New York at Stony Brook in 1997. From 1994 to 1999, he was with the Department of Physics at SUNY Stony Brook, working on the design and testing of integrated circuits based on Josephson junctions.

Frank Libsch received his M.S. and Ph.D. degrees in Electrical Engineering at the Sherman Fairchild Center for Solid-State Studies at Lehigh University, Bethlehem, Pennsylvania, in 1984 and 1988, respectively. He subsequently joined IBM at the Thomas J. Watson Research Center in Yorktown Heights, NY, where he worked on a wide range of solid state devices, circuits and display technologies. His present work involves Si and PCB integrated single- and multi-mode optical waveguides and coupling packages for high bandwidth severs and emerging technologies. He holds over 40 U.S. patents and is the author or coauthor of numerous technical publications. He is a member of the IEEE, MRS, NY Academy of Science, Sigma Xi, and SID.

Clint L. Schow joined IBM's Thomas J. Watson Research Center in 2004 as a research staff member. He is currently working on parallel optical interconnect technologies and high-speed CMOS circuits for fiber-optic data links. He received his bachelor of science degree in electrical engineering in 1994 and his MS and PhD in electrical engineering from the University of Texas at Austin in 1997 and 1999, respectively. In 1999, he joined IBM in Rochester, MN, assuming responsibility for the optical receivers used in IBM's optical transceiver business. From 2001 to 2004, he was with Agility Communications in Santa Barbara, CA, developing high-speed optoelectronic modulators and tunable laser sources for optical communications.

Vadim Heyfitch, a design engineer at Avago Technologies who holds a master of science degree in physics, has worked as a signal and power integrity lectronics engineer on designs such as server systems, memory, FPGA, E/O module, and test boards.

Vladimir Dmitriev-Zdorov is a principal engineer in the System Design Division at Mentor Graphics Corp. He has developed a number of advanced models and novel simulation methods used in the company's products. He received PhD and DSc degrees based on his work on circuit and system simulation methods. The results of his work have been published in numerous papers and conference proceedings, and a monograph.

not available at the moment of submission

Daniel Dvorscak joined ANSYS (formally Ansoft) in 2004 and focuses on circuit simulation technologies for signal integrity applications as a technical services engineer. He received his bachelor's degree in electrical engineering from Renesselear Polytechnic Institute in May of 1999. He then worked for Compaq/Hewlett-Packard as a signal integrity engineer, working on the AlphaServer product line.

Michael Tsuk joined ANSYS (formerly Ansoft) in 2003 and has focused on transient simulation of frequency-dependent data, along with other applications of advanced algorithms to engineering simulation problems, as a principal R&D engineer. Tsuk received his bachelor's, master's, and PhD degrees from the Massachusetts Institute of Technology in 1984, 1986, and 1990, respectively. In 1990, he joined Digital Equipment Corp., developing its in-house electromagnetic CAD tools, and continued that work through the Compaq and Hewlett-Packard mergers.