2013 Paper Awards Finalists

Category/Track	Title	Speakers/Co-Authors
Analog, Mixed-Signal, and RF Design and Verification	Applying Microwave Techniques to Digital Systems: A Simple Case Study	Andrew Becker, Cray; Michael Higgins, Cray; Michael Steinberger, SiSoft; Paul Wildes, SiSoft
Analog, Mixed-Signal, and RF Design and Verification	Enabling DFT Logic and Timing Verification in Mixed-Signal Designs	Bing Chuang, Rambus ; Sumit Vishwakarma, Synopsys; Kaneez Tumpa, Rambus
Chip-Level Design for Signal/Power Integrity	Power/Ground Bump Optimization Technique on Early Design Stage	Youngsoo Lee, Samsung Electronics; Dongyoun Yi, Samsung Electronics
Chip-Level Design for Signal/Power Integrity	3D Si Interposer Design and Electrical Performance Study	Mandy (Ying) Ji, Rambus; Ming Li, Rambus; Julia Cline, Rambus; David Secker, Rambus; Kevin Cai, Rambus; John Lau, ITRI; Pei-Jer Tzeng, ITRI; Chau-Jie Zhan, ITRI; Ching-Kuan Lee, ITRI
Designing with Programmable Architectures	A Rapid Prototyping of FPGA-Based Duobinary Transmitter/Receiver for High-Speed Electrical Backplane Transmission	Ashraf Umar, Penn State Harrisburg; Aldo Morales, Penn State Harrisburg; Sedig Agili, Penn State Harrisburg; Mike Resso, Agilent; Marcel Christoph Welpot, Penn State Harrisburg
Electromagnetic Compatibility and Interference	Validating EMC Simulation by Measurement in Reverberation Chamber	Xiaoxia Zhou, Cisco Systems; Jing Li, Cisco Systems; Hongmei Fan, Cisco Systems; Alpesh Bhobe, Cisco Systems; Kam Taunk, Cisco Systems; Jinghan Yu, Cisco Systems; Philippe Sochoux, Cisco Systems
Electromagnetic Compatibility and Interference	Effects of Nearby Ground Vias on High Speed Single-Ended and Differential Signals	Alma Jaze, IBM; Bruce Archambeault, IBM; Sam Connor, IBM
High-Speed Serial Design	Signal and Power Integrity (SPI) Co-Analysis for High-Speed Communication Channels	Renato Rimolo-Donadio, IBM T.J. Watson Research Ctr; Xiaomin Duan, Technical University of Hamburg-Harburg; Young H. Kwark, IBM T.J. Watson Research Center; Xiaoxiong Gu, IBM T.J. Watson Research Center; Christian W. Baks, IBM T.J. Watson Research Center; Sebastian Mueller, Technical University of Hamburg-Harburg; Thomas-Michael Winkel, IBM Research and Development; Thomas Strach, IBM Research and Development; Lei Shan, IBM T.J. Watson Research Center; Hubert Harrer, IBM Research and Development; Christian Schuster, Technical University of Hamburg-Harburg
High-Speed Serial Design	Time-Domain and Statistical Model Development, Correlation, and Analysis Methods for High-Speed SerDes	Xingdong Dai, LSI; Fangyi Rao, Agilent Technologies; Shiva Prasad Kotagiri, LSI; John Baprawshi, LSI; Cathy Ye Liu, LSI
High-Speed Serial Design	Channel Operating Margin (COM): Evolution of Channel Specifications for 25 Gbps and Beyond	Richard Mellitz, Intel; Adee Ran, Intel; Mike Li, Altera; Vira Ragavassamy, Intel
High-Speed Serial Design	Beyond 25 Gbps: A Study of NRZ and Multi-Level Modulation in Alternative Backplane Architectures	Adam Healey, LSI ; Chad Morgan, TE Connectivity; Megha Shanbhag, TE Connectivity
High-Speed Signal Processing, Equalization and Coding	Design and Analysis of a High-Speed Parallel Interface for 16 Gbps Coded Differential Signaling	Wendemagegnuhu T. Beyene, Rambus; Amir Amirkhany, Rambus; Kambiz Kaviani, Rambus; Aliazam Abbasfar, Rambus
High-Speed Signal Processing, Equalization and Coding	Partial Response and Noise Predictive Maximum Likelihood (PRML/NPML) Equalization and Detection for High-Speed Serial Link Systems	Pervez Aziz, LSI; Cathy Ye Liu, LSI; Adam Healey, LSI
Jitter, Crosstalk, and Noise Analysis	Dramatic Noise Reduction Using Guard Traces with Optimized Shorting Vias	Eric Bogatin, Bogatin Enterprises; Lambert Simonovich, Lamsim Enterprises
Jitter, Crosstalk, and Noise Analysis	Measurement-Based Simulation: Increasing IBIS-AMI Model Accuracy with Data from Lab Measurements	Michael Steinberger, SiSoft; Paul Wildes, SiSoft; Anders Ekholm, Ericsson AB; Nicke Svee, Ericsson AB
Parallel and Memory Interface Design	DDR Memory Channel Design from Passive Stub Equalizer Perspective	Jongbae Park, Intel; Myunghyun Ha, Intel; Qin Li, Intel
Parallel and Memory Interface Design	Accurate Receiver Clock Positioning in High-Speed Parallel Buses	Arun Vaidyanath, Rambus; Dan Oh, Altera; Christopher Madden, Rambus; Yohan Frans, Rambus; Woopoung Kim, Qualcomm
PCB Design Tools and Methodologies	Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling	Xiang Li, Intel; James McCall, Intel
PCB Materials, Processing and Characterization	Analytic Solutions for Periodically Loaded Transmission Line Modeling	Priya Pathmanathan, Intel; Paul Huray, University of South Carolina; Steve Pytel, ANSYS
PCB Materials, Processing and Characterization	Which One Is Better? Comparing Options to Describe Frequency Dependent Losses	Eric Bogatin, Bogatin Enterprises; Don DeGroot, CCN Labs; Paul Huray, University of South Carolina; Yuriy Shlepnev, Simberian
Power Integrity and Power Distribution Network Design	Innovative PDN Design Guidelines for Practical High-Layer-Count PCBs	Ketan Shringarpure, Missouri S&T; Siming Pan, Cisco Systems; Jingook Kim, UNIST; Brice Achkir, Cisco Systems ; Bruce Archambeault, IBM; Jun Fan, Missouri S&T; James Drewniak, Missouri S&T
Power Integrity and Power Distribution Network Design	Memory Interface On-Chip PDN Noise Characterization, Modeling and Its Impact on Timing	Bipin Dhavale, Altera; June Feng, Altera; Yuri Tretiakov, Altera; Janani Chandrasekhar, Altera; Shishuang Sun, Altera; Mayra Sarmiento, Altera; Sunitha Chandra, Altera; Daniel Chow, Altera, Aman Aflaki, Altera
Power Integrity and Power Distribution Network Design	Power-Signal Co-integrity Design for Multi-Gbps Low-Power DDR3 Mobile Platforms	Weiliang Yuan, Samsung Electronics; Seungbae Lee, Samsung Electronics; Chanmin Jo, Samsung Electronics; Woonghwan Ryu, Samsung Electronics; Sangmin Lee, Samsung Electronics
Signal Propagation Analysis Techniques	A Reverse Nyquist Approach to Understanding the Importance of Low-Frequency Information in Scattering Matrices	Daniel Dvorscak, ANSYS; Michael Tsuk, ANSYS
System Co-Design: Chip/Package/Board	A Reusable Generic Platform for Validation and Characterization of High Speed Mixed Signal Designs	Sanku Mukherjee, Rambus; Narayanan Mayandi, Rambus; Brian Tsang, Rambus; Sreeja Menon, Rambus; Benedict Lau, Rambus; Norman Chan, Rambus; Arul Sendhil, Rambus
System Co-Design: Chip/Package/Board	Using Power Aware IBIS v5.0 Behavioral IO Models to Simulate Simultaneous Switching Noise	Romi Mayder, Xilinx; Chris Wyland, Xilinx; Bradley Brim, Cadence; Yingxin Sun, Cadence
Test and Measurement Methodology	High-Throughput, High-Sensitivity Measurement of Power Supply-Induced Bounded, Uncorrelated Jitter in Time, Frequency, and Statistical Domains	Daniel Chow, Altera; Yujeong Shim, Altera; Shishuang Sun, Altera
Test and Measurement Methodology	Terabit/s Packaging Design for Testing of High-Speed Integrated Circuits	Christian W. Baks, IBM T.J. Watson Research Center; Renato Rimolo-Donadio, IBM T.J. Watson Research Center; Young H. Kwark, IBM T.J. Watson Research Center; Fuad Doany, IBM T.J. Watson Research Center; Xiaoxiong Gu, IBM T.J. Watson Research Center; Daniel Kuchta, IBM T.J. Watson Research Center; Benjamin Lee, IBM T.J. Watson Research Center; Alexander Rylyakov, IBM T.J. Watson Research Center; Frank Libsch, IBM T.J. Watson Research Center; Clint Schow, IBM T.J. Watson Research Center