J. Thomas Pawlowski is a Fellow and Chief Technologist with Micron's Architecture Development Group. His responsibilities include evaluating new technologies/investments, exploring new memory and system architectures, and providing guidance to many technical teams, both internally and external to Micron.
Mr. Pawlowski's experience includes the creation or co-creation of numerous groundbreaking memory architectures and concepts, such as: synchronous pipelined SRAM, hierarchical cache systems, Zero Bus Turnaround SRAM, the first double data rate memory (starting with SRAM and then its subsequent proliferation to DRAM and NAND technologies), PSRAM, high-speed NAND, the first double address rate memory, the first quad data rate memory, the first multi-channel memory, memories on SERDES buses, the first DRAM to exceed SRAM performance (RLDRAM), refresh and error correction schemes for memory subsystems, the architectural roots of Micron's HMC device, the first dedicated hardware architecture of Micron's newly announced nondeterministic Automata Processor, and other projects still in development.
Mr. Pawlowski earned a Bachelor of Applied Science degree in Electrical Engineering, summa cum laude, from the University of Waterloo in Canada. He also holds approximately 150 U.S. and international patents and serves on several advisory boards, including the Exascale Grand Challenge EAB.
In his spare time, Mr. Pawlowski designs and builds loudspeakers and custom tools, and he has completed 60% of the design of a revolutionary electric car concept.