• Conference
    Jan 31-Feb 2, 2017
  • Expo
    Feb 1-2, 2017
  • Santa Clara, CA
    Santa Clara Convention Center

2017 Conference Overview

The DesignCon Technical Conference Program consists of 14 tracks covering all aspects of electronic design, from chips through boards and systems.

With more than 100 technical paper sessions, panels, and tutorials; conference attendees gather the latest theories, methodologies, applications, and advanced design tools related to signal integrity, power integrity, jitter, crosstalk, test and measurement, parallel and memory interface design, ICs, semiconductor components, and more.
Get your pass.


Tuesday, January 31:
9:00 AM - 6:00 PM

Wednesday, February 1:
8:00 AM - 5:00 PM

Thursday, February 2:
8:00 AM - 5:00 PM

DesignCon 2017 Tracks

Chip and package level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the chip & package level, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Explore the Conference


Selected through a rigorous review process conducted by the Technical Program Committee, DesignCon speakers constitute an elite group of practicing engineers, offering leading-edge case studies, technology innovations, practical techniques, design tips and application overviews.


Prior to the conference, you may need to convince your manager(s) to invest professional development funds in your attendance. Here are several documents you can use that will help your efforts.


Each year, DesignCon hosts 3 keynotes from industry luminaries. Stay tuned as we reveal these insightful experts and highlight their contributions to the community.


Browse the full agenda by day, track and pass type, then customize and export your schedule or access it through the DesignCon mobile app.