• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

Conference Overview

1 Pass. 14 Tracks.

DesignCon offers an in-depth, three-day conference program curated by our Technical Program Committee (TPC) — an expert panel of more than 90 industry professionals. With over 100 technical paper sessions, panels, and tutorials spanning 14 tracks, DesignCon's educational content covers all aspects of electronic design, including signal and power integrity; system co-design; and test and measurement methodologies. PLUS! New this year: Acquire an IEEE credit for every hour you spend at the conference. Learn more.

Conference Hours

Tuesday, January 30
9:00 a.m.–6:00 p.m.

Wednesday, January 31
8:00 a.m.–4:45 p.m.

Thursday, February 1
8:00 a.m.–4:45 p.m.

Conference Tracks

Select a track name for more details.

Die, interposer, and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, and packaging levels, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Sample topics

  • Signal integrity (SI), power integrity (PI), and power delivery network (PDN) considerations in chip designs
  • Implications of chip-level decisions on systems design (e.g. frequency, timing, design overhead, voltage)
  • High-speed I/O design
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-gating design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • Clock and reset strategies
  • 2.5D/3D interconnects and interposer design
  • Through-silicon vias (TSV)
  • SIP partition and IP integration
  • On-chip and chip-to-chip interconnect design and analysis
  • Pre-silicon validation and verification
  • Post-silicon validation and verification

Achieving first-pass design success with today's complex systems requires ever improving simulation approaches. Chip-to-chip data channels, clocks, and power delivery solutions each have specialized modeling requirements that must be met to accurately predict and deliver expected system performance while accelerating design cycles. The use of IBIS-AMI models, for example, must be done with confidence that the model is adequate, awareness of potential model limitations, and full exploitation of the model's features and benefits. This track addresses challenges and solutions for design and verification that may involve various analog and algorithmic modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability.

Sample topics

  • IBIS-AMI model generation, validation and simulation strategies
  • Practical electrical vs. algorithmic partitioning for successful modeling
  • Effective I/O modeling of exotic modulation (PAM, duo-binary etc.)
  • Handling PVT corners within IBIS and AMI models
  • Power-aware IBIS modeling for SSO simulation.
  • Guidelines for achieving consistent results with different simulation tools.
  • Faster channel simulation approaches; SPICE, Statistical, System
  • SPICE vs. IBIS modeling and SPICE-to-IBIS tradeoffs
  • AMI model extraction from data-sheet parameters.
  • IBIS-AMI model quality and silicon correlation methodologies
  • Methods for converting Verilog or MATLAB models to IBIS-AMI
  • Design and IBIS simulation with repeaters and retimers
  • Case studies of achieving trustworthy compliance testing through simulation
  • Machine learning approaches for behavioral modeling
  • Mixed-signal behavioral models for SERDES phase-locked loops
  • Approaches for system-level modeling of I/O buffers and voltage regulators
  • Behavioral modeling of clock jitter and phase noise
  • Simulation of reliability gain/loss by different power topology selection
  • Digital Controllers and compensators for Voltage control, modeling and correlation.

Integrating photonics into electrical design to meet higher data rates presents unique technical and design challenges. Emerging modulation schemes coupled with high channel losses, nonlinear optics, use of complex equalization, re-timers, and integration of FEC within the receiver are just a few technical complexities. Integrating photonics brings other new challenges in terms of power, thermal, small footprint, high density, etc. — considerations the engineers need to solve to enable high-performance and high-data-rate designs.

Sample topics

  • Techniques to bring together high-speed electrical and high-speed optical circuits
  • Measurement and testing of optical/electrical ICs
  • Dealing with coexistence issues when integrating optical and/or wireless transmission, e.g. EMI, integration
  • Photonic ICs
  • Microwave photonics
  • Photonic interconnects
  • Photonic integration and packaging design
  • Link design
  • Link impairments
  • Electro-optics
  • Optical signal processing
  • Passive components for 100 Gbps/400 Gbps optical communications.
  • Wireless and optical network convergence
  • Layout considerations for RF circuits, photonic circuits
  • Silicon nanophotonics
  • High-speed wireless options
  • FCC qualification; interference mitigation Integrated optical links, optical interconnects
  • Integration of optical subsystems

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

Sample topics

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • PCB/package/chip/device power modeling
  • Interaction of protection devices
  • End-to-end link modeling
  • New technology design, including IoT design and 5G system co-design
  • First- and second-level interconnect analysis
  • Sub-system interaction
  • System-level power and signal integrity
  • Buffer modeling for system simulation
  • System co-design for high-speed signaling
  • I/O interoperability
  • Merging of chip design and package design
  • Mixed-signal system design
  • Multi-voltage design
  • Package modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP) design
  • 3D/2.5D on-chip interconnect design and analysis
  • Performance trade-offs: electrical, mechanical, thermal

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

Sample topics

  • Advanced interconnects including conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Microvias, RF vias and thermal vias
    • High aspect-ratio vias
    • What materials should I choose?
    • Routing Techniques
    • Materials for optical waveguides
    • Sockets and connectors
  • Advanced laminate and PCB processing
    • Fine registration improvements
    • Advanced Stub mitigation including backdrilling
    • Embedded devices
    • Passive and active devices
    • Embedded optical channels
    • Power delivery and decoupling
  • 3D Printing
  • Next Generation Materials
    • Advances in low loss laminates
    • Advances in copper surfaces
    • Advances in thin dielectrics
  • Rigid-flex and multilayer flex circuit materials, design and manufacturing
  • Glass weave effects on signal quality and techniques to mitigate
  • Materials characterization and modeling
  • Creative techniques to implement next generation technology in high rate production
  • Trade-offs in SI/PI/Timing Integrity
    • Impact on costs and techniques to reduce cost
  • Thermal characterization and modeling
  • How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths

High-speed data transfer up to 56 Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112 Gbps? Can PCB support high-current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization tools, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

Sample topics

  • PHY channel development and characterization for 56G and 112G PAM4 modulated signaling
  • Electrical, optical, and mechanical co-design: choices and trade offs
  • How to simulate PI and SI on a PCB
  • PI and SI simulation automation and screening
  • EM modeling of PCB traces/vias, sockets, and connectors
    • EM Modeling and PCB/PCB System mode conversion
  • Board layout techniques for PI and SI
  • Thermal and noise interaction between digital interfaces and subsystems
    • Thermal Modeling of PCB/PCB System performance
  • DC power supply/conversion and PCB co-simulations
  • Via pin-field design and optimization
  • Case studies (caution: must be non-commercial)
  • Design challenges for wearable electronics
    • Material/dielectric modeling and characterization
    • Simulation accounting for change in material e.g., when flexed or bent
  • Advances in high-speed conductive surface modeling
    • EM toolsets and EDA support
    • Copper roughness and characterization

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in IO interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, and form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various IO interfaces.

Sample topics

  • 2.5D/3D/SiP interface
    • HBM, HMC and WideIO interfaces
    • Proprietary or emerging 2.5D/3D/SiP IO interfaces
  • Memory interface
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
    • NV memory
    • Emerging memory interface (optical memory)
  • High-speed parallel interface
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
    • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
    • Low-power designs
  • Signal/power integrity simulation
    • Supply noise induced clock and data jitter analysis
    • Channel crosstalk, simultaneous switching noise, and statistical timing models

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

Sample topics

  • Backplane and cable interconnect
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Loss and timing budgets for electrical or optical links
  • Physical modeling and simulation
  • Signal integrity for backplanes and cables
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • PAM-N vs NRZ system trade-offs/case studies
  • Optical waveguide channels
  • Machine learning techniques and applications for serial link optimization

Jitter, noise, crosstalk, ISI, and reflection cause errors. This track covers techniques for measuring, analyzing, and minimizing BER (bit error ratio), SER (symbol error ratio), and FER (frame error ratio), including simulation and modeling of signal impairments and techniques that optimize performance.

Sample Topics:

  • Error ratio, SNDR (signal-to-noise-distortion ratio), level-mismatch/non-linearity and distortion analysis, measurement, and simulation
  • Measurement and estimation of total jitter/total noise, eye width, eye height, and eye closure defined at a BER
    • Jitter and noise simulation, analysis, and measurement
    • Stochastic and deterministic, correlated and uncorrelated jitter, noise, crosstalk, and ISI (inter-symbol interference) modeling techniques
  • PAM4 signal measurement, analysis, and BER/SER/FER minimization
  • Machine learning and AI (artificial intelligence) techniques for minimizing noise, jitter, and BER
  • Relationship between S-parameters and time domain errors
  • Skin-effect, dielectric loss, surface roughness, and ISI measurement, analysis, and equalization
  • Jitter and noise test and measurement for diagnostics and standards compliance
  • Time/frequency domain, phase noise, and white and colored jitter spectrum analysis and prediction
  • Stressed eye interference and jitter tolerance testing techniques
  • Close eye analysis via CTLE/FFE/DFE
  • Embedded/forward clocking and related jitter mitigation techniques
  • BER/SER/FER analysis, modeling, and optimization in the presence of FEC (forward error correlation) for Gaussian and burst errors

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Sample topics

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithms, modeling and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction)
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • High-speed channel de-embedding and modeling
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Measurement verification
  • Multi-level signaling
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling.
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
  • Back-channel training methods and performance
  • Machine learning applied to signal processing algorithms and architectures

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling, and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

Sample topics

  • System level PDN design strategy
    • Signal/power integrity co-design
    • Chip/package/board decoupling optimization
    • PDN performance versus cost, size, yield, reliability, etc.
    • PDN specifications
    • PDN modeling and simulation
    • PDN Measurements and correlation
    • System noise modeling and mitigation
    • Supply noise induced jitter analysis and optimization
  • Chip-level power distribution and regulation
    • On-chip power grid
    • Dynamic and static voltage variations
    • On-chip regulator, multi-voltage, and power-gating design
  • Power supply design
    • DC/DC converter and VRM design including GaN technology
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management for portable & mobile electronics
    • Wireless power transfer
    • Digital control loops
    • Low-voltage, high-power designs
    • VRM modeling and simulation

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

Sample topics

  • Design techniques to reduce or eliminate sources of EMI
  • EMI radiation and suppression
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Pre-qualification testing for emissions
  • Near-field coupling and crosstalk
  • Noise characterization and containment
  • Emissions and interference modeling
  • Shielding and package design
  • EMI measurement: near-field scanning and far-field correlation
  • EMI for high-density multi-port systems
  • EMI system susceptibility
  • ESD modeling

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Sample topics

  • Measurement methodologies for Signal Integrity, Power Integrity, and EMI/EMC
  • Standards-based measurement methods for compliance with PAM4, Ethernet, PCIe, USB, DDR, etc.
  • S-Parameter quality, causality, and passivity of measurement calibration methods
  • Passive device-measurement methods for on-die, package, connector, board testing
  • Power supply noise measurement methods for dynamic load response, ripple injection…
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Signal integrity of fixture design for PCB, connectors, package, on-die, measurements.
  • Fixture de-embedding techniques including EM-solver and measure based models
  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
  • Measurement methods and instrumentation architecture
  • ATE and sub-systems design validation and production at speed testing

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

Sample topics

  • Signal integrity analysis with RF/Microwave techniques
  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • RF/microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • Dielectric, conductor and conductor roughness model parameters identification
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpintines)

Welcome Reception

Kick off the show with this exclusive networking event. Enjoy complimentary snacks and drinks on Tuesday, January 30, from 6 to 8:00 p.m. at the Santa Clara Ballroom at the Hyatt Santa Clara. Open to all-access, two-day, and boot camp pass holders, as well as media representatives, speakers, TPC members, and exhibitors. (Badge required for entry.)
Sponsored by: Keysight Technologies

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