• Conference
    Jan 31-Feb 2, 2017
  • Expo
    Feb 1-2, 2017
  • Santa Clara, CA
    Santa Clara Convention Center

2017 Conference Overview

The DesignCon Technical Conference Program consists of 14 tracks covering all aspects of electronic design, from chips through boards and systems.

With more than 100 technical paper sessions, panels, and tutorials; conference attendees gather the latest theories, methodologies, applications, and advanced design tools related to signal integrity, power integrity, jitter, crosstalk, test and measurement, parallel and memory interface design, ICs, semiconductor components, and more.
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2017 CONFERENCE HOURS

Tuesday, January 31:
9:00 AM - 6:00 PM

Wednesday, February 1:
8:30 AM - 5:00 PM

Thursday, February 2:
8:30 AM - 5:00 PM

DesignCon 2017 Tracks


Chip and package level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the chip & package level, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Today’s chips and systems require new modeling and simulation approaches that have adequate accuracy to ensure design success, but give useful results quickly. Faster data channels and interfaces require specialized models that take into account analog and high-frequency effects. Yet, combining these with behavioral models (such as IBIS-AMI) for fast simulation must be done carefully to capture critical eye effects. This track addresses challenges and solutions for design and verification that may involve various modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability.

Integrating photonics into electrical design presents unique technical and practical challenges to meet high data rate requirements. PAM4 and other modulation schemes, coupled with high channel losses and nonlinear optics, demand complex equalization, re-timers and integration of FEC within the receiver. While the technical challenges are formidable, the practical power and thermal issues arising due to high density and smaller size requirements must be addressed, and will be covered in this track.

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

High-speed data transfer up to 56-Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112-Gbps? Can PCB support high current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization tools, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in IO interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, and form factor. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various IO interfaces.

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

The impact of Jitter, Noise, Crosstalk, ISI, and reflection have a detrimental impact on BER. Simulation, measurements, and analysis techniques that improve the insight and analysis of these factors to minimize system BER performance will be presented in this track.

High-speed communication systems require increasingly complex signal-processing techniques; including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

Explore the Conference


SPEAKERS

Selected through a rigorous review process conducted by the Technical Program Committee, DesignCon speakers constitute an elite group of practicing engineers, offering leading-edge case studies, technology innovations, practical techniques, design tips and application overviews.


JUSTIFICATION TOOLKIT

Prior to the conference, you may need to convince your manager(s) to invest professional development funds in your attendance. Here are several documents you can use that will help your efforts.


KEYNOTES

Each year, DesignCon hosts 3 keynote speakers from industry luminaries. Stay tuned as we reveal these insightful experts and highlight their contributions to the community.


SCHEDULE BUILDER - COMING SOON!

Browse the full agenda by day, track and pass type, then customize and export your schedule or access it through the DesignCon mobile app.