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2014 Call for Abstracts


Deadline for Abstracts: August 5, 2013
Acceptance Notifications: Late September
Papers Due: November 19, 2013

DesignCon 2014 details:
January 28-31, 2014
Santa Clara Convention Center
Santa Clara, CA

Thank you for your interest in the technical program for DesignCon 2014. The Call for Abstracts is now closed. All submissions will be reviewed by the Technical Program Committee based on the criteria below. Please expect notification as to the status of your submission in late September.

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Review Criteria

The DesignCon 2014 Technical Program Committee will review all submissions based on quality, relevance, impact, and originality. Prospective authors are welcome to reference products as long as product references add to the educational value and are presented in an appropriately non-commercial fashion.

A. Quality

DesignCon papers, panels, and tutorials should be well organized and easily understood. The abstract and summary are judged as indicators of what can be expected of the paper or session.

B. Relevance

The proposed paper, panel, or tutorial should be highly relevant to the interests of the DesignCon audience in general and the track topic in particular.

C. Impact

DesignCon papers, panels, and tutorials should contribute to the educational mission of DesignCon. Submissions reporting on important results, methodologies or case studies of special significance will be considered favorably.

D. Originality

Reports on new design methodologies, case studies for innovative designs or other novel results contribute to the DesignCon goal of providing a high-quality educational program for practicing engineers. However, outstanding proposals on “classical” topics will also be viewed favorably.

E. Commercial Content

It is acceptable to use a product in a design case study or as a proof of concept for a design methodology. Product promotion is not permitted in DesignCon technical sessions. Evidence of product promotion in a paper, panel, or tutorial proposal will lead to rejection of the proposal.

All relevant proposals—including topics other than those listed—will be considered. Submissions on related standards activities are welcome.

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DesignCon 2014 Topic Categories

Jump to a topic:

  1. Optimize Chip-Level Designs for Signal and Power Integrity
  2. Overcome Analog and Mixed-Signal Design and Verification Challenges
  3. Wireless and Photonic Design & Integration
  4. Optimize System Co-Design: Chip/Package/Board
  5. Characterize PCB Materials and Processing Characterization
  6. Apply PCB Design Tools and Methodologies
  7. Design Parallel and Memory Interfaces
  8. Optimize High-Speed Serial Design
  9. Detect and Mitigate Jitter, Crosstalk, and Noise
  10. Leverage High-Speed Signal Processing for Equalization and Coding
  11. Ensure Power Integrity in Power Distribution Networks
  12. Achieve Electromagnetic Compatibility and Mitigate Interference
  13. Apply Test and Measurement Methodology
  14. Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

1. Optimize Chip-Level Designs for Signal and Power Integrity

Chip-level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the on-chip level, from interconnect topologies, transceiver technology and design, to noise and jitter mitigation strategies.

  • Low-power strategies and implementation
  • On-chip power distribution networks
  • Clock and reset strategies
  • On-chip interconnect design and analysis
    • 3D interconnects and interposer design
    • Package-on-package
    • Through-silicon vias
    • IP interconnect and integration
  • On-chip signal and power integrity
    • Architecture impact
    • Multi-voltage, and power-gating design
    • On-die current modeling and correlation
  • High-speed I/O design
  • Silicon photonics integration
  • On-chip instrumentation and measurement
  • Pre-silicon validation and verification
  • Post-silicon validation and verification

2. Overcome Analog and Mixed-Signal Design and Verification Challenges

Today’s chips possess an abundance of analog, mixed-signal, and RF functionality necessary for intra-system and real-world interfacing. This track addresses challenges and solutions encountered in the design, verification, and system modeling of AMS & RF technology from a perspective beneficial to both chip and system design engineers.

  • Design & verification methodologies
  • Simulation algorithms and techniques
  • Mixed-signal behavioral modeling approaches
  • Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog, SystemC-AMS, etc.
  • Mixed-domain design and verification solutions
  • MEMS, electro-optics, mechatronics, etc.
  • Mixed-domain/mixed-language verification strategies
  • Analog IP: selection, integration, and modeling
  • Coverage, metrics, and closure management
  • Yield analysis, Monte Carlo methods, and optimization approaches
  • On-chip inductors: design and modeling
  • RLCK extraction: post-layout flows and strategies
  • Noise analysis and prediction: substrate, spurious, random
  • Variability effects and statistical analyses

3. Wireless and Photonic Design & Integration

The aim of this track is to provide a forum covering practices and methodologies used in emerging system designs and applications leveraging wireless and photonic technologies as media for data transmission.

  • Measurement and testing of optical/electrical ICs
  • Photonic ICs
  • Microwave photonics
  • Photonic interconnects
  • Photonic integration and packaging design
  • Link Design
  • Link impairments
  • Electro optics
  • Optical signal processing
  • Passive components for 100 Gbps/400 Gbps optical communications.
  • Wireless and optical network convergence.
  • Layout considerations such RF circuits, photonic circuits...
  • Silicon nanophotonics
  • High-speed wireless options
  • RF considerations
  • Antenna design and placement
  • FCC qualification; interference mitigation
  • Wireless test
  • 60 GHz and above based wireless communication (e.g., WiGig)

4. Optimize System Co-Design: Chip/Package/Board

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity performance optimization of Chip/Package/Board/Chip+Package+Board for modern microprocessor/digital systems.

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • PCB/package/chip/device power modeling
  • Interaction of protection devices
  • End-to-end link modeling
  • Pin-out optimization, signal fan-out
  • First- and second-level interconnect analysis
  • Sub-system interaction
  • System-level de-coupling strategy
  • System-level power and signal integrity
  • System noise modeling & mitigation
  • Buffer modeling
  • High-speed signaling, I/O interoperability
  • Integrated optical links, optical interconnects
  • Integration of optical subsystems
  • Photonic ICs
  • Merging of chip design and package design
  • Mixed-signal system design
  • Multi-voltage design
  • Package modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP) design
  • 3D/2.5D on-chip interconnect design and analysis
  • Performance trade-offs: electrical, mecahnical, thermal

5. Characterize PCB Materials and Processing Characterization

Printed circuit boards (PCBs) can no longer be viewed as passive platforms for mounting and interconnecting electronic components. This track considers how PCB materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

  • Advanced conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of low copper surface roughness
    • Microvias, RF vias & thermal vias
    • High aspect-ratio vias
  • Advanced laminate and PCB processing
    • Interlayer connectivity alternatives
    • Fine registration improvements
    • Backdrilling methods & effects
  • Embedded devices
    • Passive and active devices
    • Embedded optical channels
    • Power delivery
  • 40-Gbps PHY channel development and characterization
    • 40-Gbps channel materials and construction techniques
  • Rigid-flex and multilayer flex circuit design and manufacturing
  • Lead-free materials (RoHS)
  • Fabrication: cost vs. performance
  • Manufacturing impact on electrical properties
  • Glass weave effects on signal quality
  • Materials characterization and modeling
  • Optical waveguides
  • PCB and package considerations
  • PCB materials for power integrity
  • Sockets and connectors
  • Thermal characterization

6. Apply PCB Design Tools and Methodologies

High-speed data transfer and telecommunications are supported by PCB platforms that typically constitute over 80% of the channel length while concurrently supporting power delivery, mixed-signal requirements and full-blown serial data speeds. This track explores effective high-speed design and design choices using a wide range of E-M modeling techniques, PCB characterization tools and test platforms to optimize PCB platforms such as backplanes, mid-planes and daughter cards combined with separable interconnects and optical channels.

  • 40-Gbps PHY channel development and characterization
    • 40-Gbps channel design and characterization
  • Electrical, optical, and mechanical co-design
  • EM modeling of PCB traces and vias
  • High-density and optical interconnects
  • PCB design challenges, tools, and techniques
  • PCB test and measurement
  • Power and signal integrity for board layout design
  • Sockets and connectors
  • Via pin-field design

7. Design Parallel and Memory Interfaces

Memory and parallel interface designs continue to be challenged with complex performance requirements including bandwidth, power consumptions, and form factors. This track addresses the latest design techniques and signal and power integrity issues to meet these performance requirements for various chip-to-chip interfaces. I/O system used in 2.5D, 3D, on-chip, SiP, and MCM are covered in this track in addition to conventional on-board interface designs.

  • High-speed parallel interface design
    • Standards-based design (DDRs, LP-DDRs, GDDRs, HyperTransport 3.0, PCI-X, SPI 4.2 ...)
    • Rules-based design
    • Developing standard design specifications and budgets
    • Clocking architecture
    • Parallel interconnect signal conditioning techniques
    • Design margin vs. complexity vs. cost
    • Low-power designs
    • Developing and managing high-speed layout rules
  • Signal integrity simulation
    • High speed I/O modeling
    • Crosstalk and simultaneous switching noise impacts
    • Designing with impedance controlled buffers/on-die termination
    • Differential vs. single-ended signaling
    • Performance vs. power vs. signal integrity
    • Timing analysis methodologies
    • Statistical timing, bit-error-rate analysis
    • Parallel vs. serial interfaces
    • Jitter amplification and tracking
  • Memory interface and 3D integration
  • System/FPGA/ASIC timing closure
  • Embedded memories

8. Optimize High-Speed Serial Design

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

  • Backplane and cable interconnect
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end to end channel analysis
  • Loss and timing budgets for electrical or optical links
  • Physical modeling and simulation
  • Signal integrity for backplanes and cables
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • WDM in backplanes

9. Detect and Mitigate Jitter, Crosstalk, and Noise

The only relevant signal integrity issue is whether or not a system operates at the required bit error ratio (BER). This track concentrates on the causes of errors, including, but not limited to jitter, crosstalk, and noise, and techniques for measuring and estimating BER performance such as total jitter and BER contour.

  • Bit Error Ratio (BER) analysis and measurement
  • Total jitter defined at a BER measurement and estimation
  • Jitter simulation, analysis and measurement
  • Jitter modeling techniques (stochastic/ deterministic, correlated/uncorrelated)
  • Jitter transfer analysis methods
  • Jitter separation techniques
  • Phase noise and jitter spectrum analysis and prediction
  • Dispersion and inter-symbol interference analysis and compensation
  • Effect of crosstalk on BER
  • Crosstalk mitigation, simulation, analysis, and measurement
  • Noise analysis for diagnostics and compliance
  • Time/frequency domain translation
  • Stressed eye tolerance testing techniques
  • Embedded (or forward) clocking

10. Leverage High-Speed Signal Processing for Equalization and Coding

High-speed communication systems require increasingly complex signal processing techniques, including equalization, modulation, timing, detection and forward error-correction methods. This track covers design, modeling, analysis and implementation of such techniques.

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithm, modeling and realization
  • Digital pre-emphasis and equalization
  • Error-correction coding
  • End-to-end channel analysis
  • Eye diagram compliance testing
  • High-speed channel de-embedding and modeling
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • Measurement verification
  • Multi-level signaling
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling.
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms

11. Ensure Power Integrity in Power Distribution Networks

Power Integrity, distribution and management are essential for system functionality and performance. This track addresses power regulation; power distribution network design, modeling and analysis on boards, packages, and silicon; and it emphasizes the modeling and analysis of supply noise and its impact on overall system performance.

  • Power systems design
    • DC/DC converter design
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management
  • Chip-level power distribution and regulation
    • Charge delivery analysis
    • On-chip regulator, multi-voltage, and power-gating design
  • System-level designs
    • Power integrity optimization
    • Chip/package/board power integrity specification and correlation
    • Signal/power integrity co-design
    • Simultaneous switching noise (SSN) suppression
    • Chip/package/board decoupling optimization
    • Jitter analysis and optimization of the power integrity impact

12. Achieve Electromagnetic Compatibility and Mitigate Interference

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

  • EMI radiation and suppression
  • ESD compliance and testing
  • Mixed-signal design issues
  • RF interference (RFI)
  • Near-field coupling & crosstalk
  • Noise characterization & containment
  • Emissions & interference modeling
  • Shielding & package design
  • Signal encoding & emission reduction
  • Differential to common-mode conversion
  • EMI measurement: near-field scanning for far-field estimation
  • EMI for high-density multi-port systems
  • EMI system susceptibility
  • System radiated and conducted emissions
  • Safety and compliance of power networks

13. Apply Test and Measurement Methodology

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

  • Metrology of the measurements
    • Instrumentation performance and measurement errors
    • Resolution & sensitivity
    • Algorithms for accuracy & resolution improvement
    • Calibration & accuracy
  • Methods and system architecture
    • ATE and subsystems
    • Automatic test pattern generation
    • Boundary scan, JTAG & I-JTAG test methods
    • Fluctuations, noise, jitter transformation
  • Active/passive device-measurement methods
    • Analog, mixed signal & RF testing
    • On-die instrumentation
    • SoC testing: memory, IP
    • Package, connector, board testing
    • Testing gigabit I/O
  • Fixture de-embedding methodologies
    • Signal integrity and fixture de-embedding
    • 3D-solver and measure-based test fixture design methods
    • Backplane/pin signal integrity
    • Chip/Package/Board/System measurement methods
    • Separation effects of decoupling, power, signal integrity
    • Silicon characterization/de-embedding
    • Probing & on-wafer measurements
  • Advanced measurements & DFM
    • Yield analysis & yield enhancement
    • Fault modeling & failure analysis
    • Prototyping
    • Test coverage

14. Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

Analysis of signals on interconnects with high data rates is evolving to include the extension of techniques originally developed for digital and RF/microwave systems. This track covers signal integrity analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broad-band interconnect systems
  • RF/Microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy)
  • Material parameters identification
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
  • THz and optical interconnects