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2015 Call for Abstracts

THE 2015 CALL FOR ABSTRACTS IS CLOSED

Thank you to all of those who submitted proposals to speak at DesignCon 2015. The Technical Program Committee is currently conducting their review and status notifications will be sent out in early September. Good luck!

Deadline for Abstracts: July 18, 2014
Acceptance Notifications: Early September
Papers Due: November 10, 2014
 

DesignCon 2015 details:
January 27-30, 2015
Santa Clara Convention Center
Santa Clara, CA

 

DesignCon 2015 Topic Categories

Jump to a topic:

  1. Optimize Chip-Level Designs for Signal and Power Integrity
  2. Overcome Analog and Mixed-Signal Modeling and Simulation Challenges
  3. Wireless and Photonic Integration
  4. System Co-Design: Chip/Package/Board: Modeling and Simulation
  5. Characterize PCB Materials and Processing Characterization
  6. Apply PCB Design Tools
  7. Design Parallel and Memory Interfaces
  8. Optimize High-Speed Serial Design
  9. Detect and Mitigate Jitter, Crosstalk, and Noise
  10. Leverage High-Speed Signal Processing for Equalization and Coding
  11. Ensure Power Integrity in Power Distribution Networks
  12. Achieve Electromagnetic Compatibility and Mitigate Interference
  13. Apply Test and Measurement Methodology
  14. Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

1. Optimize Chip-Level Designs for Signal and Power Integrity

Chip-level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the on-chip level, from interconnect topologies, transceiver technology and design, to noise and jitter mitigation strategies.

  • Signal integrity (SI), power integrity (PI), and PDN considerations in chip designs
  • Implications of chip level decisions on systems design (e.g. frequency, timing, design overhead, voltage)
  • High-speed I/O design
  • On chip instrumentation and measurement
  • On chip current modeling and correlation
  • On chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-gating design for SOCs and circuit level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques
  • Simultaneous switching noise and crosstalk suppression techniques
  • Clock and reset strategies
  • 2.5D/3D interconnects and interposer design
  • Through-silicon vias
  • SIP partition and IP integration
  • On-chip and chip-to-chip interconnect design and analysis
  • Pre-silicon validation and verification
  • Post-silicon validation and verification
 

2. Overcome Analog and Mixed-Signal Modeling and Simulation Challenges

As capabilities expand and complexity grows, today’s chips and systems require new modeling and simulation approaches that ensure design success, but give useful results in a reasonable amount of time. Faster I/Os and waveforms, as well as RF, MEMS, and sensor components require specialized models that take into account analog and high-frequency effects. Yet, mixing these with other models for simulation must be done efficiently to capture critical effects and still give quick answers. This track addresses challenges and solutions for design and verification that may involve various modeling abstractions and simulation approaches to predict critical aspects of system performance.

  • Statistical eye (StatEye) analysis approaches
  • IBIS-AMI model generation and validation strategies
  • SPICE vs. IBIS modeling and SPICE-to-IBIS
  • Fast SSO simulation and modeling methods.
  • HDL vs. FastSPICE vs. SPICE for AMS
  • Converting Verilog or MATLAB models to IBIS-AMI
  • Fast simulation of package models based on scattering and broadband network parameters
  • Using X-parameters for nonlinear power amplifier modeling
  • Modeling approaches for GaN, SiC, and GaAs devices for power and switching behavior
  • Mixed-signal behavioral models for SERDES phase-locked loops
  • Best practices and tradeoffs between digital Verilog vs. Verilog-AMS
  • Modeling approaches for RF devices for successful system design and integration
  • Successful system design and verification with MEMS accelerometers, CMOS Imaging sensors, or touchscreen technologies
  • Mixed time/frequency analysis approaches
  • Behavioral modeling of clock jitter and phase noise for simulation and verification.
  • How to integrate analog/mixed-signal circuitry into a system design
  • Design solutions for achieving adequate dynamic range, linearity, and sensitivity from audio to RF
  • Effect of new materials in analog/mixed-signal designs: e.g. silicon carbide, GaN
 

3. Wireless and Photonic Integration

The aim of this track is to provide a forum covering practices and methodologies used in emerging system designs and applications leveraging wireless and photonic technologies as media for data transmission. There are many challenges in system integration, especially for signal integrity and power integrity. This track looks at what happens when multiple data transmission technologies converge in one design.

  • Techniques to bring together high-speed electrical and high-speed optical circuits
  • Measurement and testing of optical/electrical ICs
  • Dealing with coexistence issues when integrating optical and/or wireless transmission, e.g. EMI, integration
  • Photonic ICs
  • Microwave photonics
  • Photonic interconnects
  • Photonic integration and packaging design
  • Link Design
  • Link impairments
  • Electro optics
  • Optical signal processing
  • Passive components for 100 Gbps/400 Gbps optical communications.
  • Wireless and optical network convergence
  • Layout considerations for RF circuits, photonic circuits
  • Silicon nanophotonics
  • High-speed wireless options
  • Making wireless technology work with digital systems in terms of signal integrity
  • Antenna design and placement
  • FCC qualification; interference mitigation Integrated optical links, optical interconnects
  • Integration of optical subsystems
 

4. Optimize System Co-Design: Chip/Package/Board

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • PCB/package/chip/device power modeling
  • Interaction of protection devices
  • End-to-end link modeling
  • Pin-out optimization, signal fan-out
  • First- and second-level interconnect analysis
  • Sub-system interaction
  • System-level power and signal integrity
  • Buffer modeling
  • High-speed signaling, I/O interoperability
  • Merging of chip design and package design
  • Mixed-signal system design
  • Multi-voltage design
  • Package modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP) design
  • 3D/2.5D on-chip interconnect design and analysis
  • Performance trade-offs: electrical, mechanical, thermal
 

5. Characterize PCB Materials and Processing Characterization

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

  • Advanced conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Microvias, RF vias and thermal vias
    • High aspect-ratio vias
    • What materials should I choose?
  • Advanced laminate and PCB processing
    • Interlayer connectivity alternatives
    • Fine registration improvements
    • Backdrilling methods and effects
  • Embedded devices
    • Passive and active devices
    • Embedded optical channels
    • Power delivery
  • 40-Gbps PHY channel development and characterization
  • Rigid-flex and multilayer flex circuit design and manufacturing
  • Lead-free materials (RoHS)
  • Fabrication: cost ,performance, reliability trade offs
  • Manufacturing impact on electrical properties
  • Determining material properties
  • Glass weave effects on signal quality
  • Materials characterization and modeling
  • Optical waveguides
  • PCB and package considerations
  • PCB materials for high-speed power integrity
  • Sockets and connectors
  • Reducing the Q of PCB planes
  • Thermal characterization
 

6. Apply PCB Design Tools

High-speed data transfer and telecommunications are supported by PCB platforms that typically constitute more than 80% of the channel length while concurrently supporting power delivery, mixed-signal requirements and full-blown serial data speeds. This track explores effective high-speed design and design choices using a wide range of E-M modeling techniques, PCB characterization tools, and test platforms to optimize PCB platforms such as backplanes, mid-planes, and daughter cards combined with separable interconnects and optical channels.

  • 40-Gbps PHY channel development and characterization
  • Electrical, optical, and mechanical co-design: choices and trade offs
  • How to simulate PI and SI on a PCB
  • EM modeling of PCB traces and vias
  • PCB design challenges, tools, and techniques
  • PCB test and measurement
  • Board layout techniques for power and signal integrity
  • Thermal and noise interaction between digital interfaces and subsystems
  • Sockets and connectors
  • Via pin-field design
  • Case studies (caution: must be non-commercial)
  • Design challenges for wearable electronics
    • Material/dielectric modeling and characterization
    • Simulation accounting for change in material e.g., when flexed or bent
  • Advances in high-speed conductive surface modeling
    • EM toolsets and EDA support
    • Copper roughness
    • Characterization
 

7. Design Parallel and Memory Interfaces

Memory and parallel interface designs continue to be challenged with complex performance requirements including bandwidth, power consumptions, and form factors. This track addresses the latest design techniques and signal and power integrity issues to meet these performance requirements for various chip-to-chip interfaces. I/O system used in 2.5D, 3D, on-chip, SiP, and MCM are covered in this track in addition to conventional on-board interface designs.

  • High-speed parallel interface design
    • Standards-based design (e.g. DDRs, LP-DDRs, GDDRs, HyperTransport 3.0, PCI-X, SPI 4.2)
    • Rules-based design
    • Developing standard design specifications and budgets
    • Clocking architecture
    • Parallel interconnect signal conditioning techniques
    • Design margin vs. complexity vs. cost
    • Low-power designs
    • Developing and managing high-speed layout rules
  • Signal integrity simulation
    • High speed I/O modeling
    • Crosstalk and simultaneous switching noise impacts
    • Designing with impedance controlled buffers/on-die termination
    • Differential vs. single-ended signaling
    • Performance vs. power vs. signal integrity
    • Timing analysis methodologies
    • Statistical timing, bit-error-rate analysis
    • Parallel vs. serial interfaces
    • Jitter amplification and tracking
  • Memory interface and 3D integration
    • WideIO, HBM, and HMC memory interfaces
  • Proprietary or emerging 2.5D and 3D I/O interfaces
  • Mobile memory design
    • LP-DDRs ,DDR-NAND, e.MMC, UFS
    • Performance/power tradeoffs
    • Design for harsh environments
  • System/FPGA/ASIC timing closure
  • Embedded memories
 

8. Optimize High-Speed Serial Design

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

  • Backplane and cable interconnect
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Loss and timing budgets for electrical or optical links
  • Physical modeling and simulation
  • Signal integrity for backplanes and cables
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • PAM-4 vs NRZ system trade-offs/case studies
  • WDM in backplanes
 

9. Detect and Mitigate Jitter, Crosstalk, and Noise

The only relevant signal integrity issue is whether or not a system operates at the required bit error ratio (BER). This track concentrates on the causes of errors, including, but not limited to jitter, crosstalk, and noise, and techniques for measuring and estimating BER performance such as total jitter, eye height, and BER contour.

  • Bit error rate (BER) analysis and measurement
  • Measurement and estimation of total jitter, eye opening, and eye height defined at a BER
    • Jitter simulation, analysis, and measurement
    • Jitter modeling techniques (stochastic/ deterministic, correlated/uncorrelated)
  • End-to-end performance analysis and simulation-measurement consistency
  • Dispersion and inter-symbol interference analysis and compensation
  • Crosstalk mitigation, simulation, analysis, and effect on BER
  • Noise analysis for diagnostics and compliance
  • Time/frequency domain, phase noise, and jitter spectrum analysis and prediction
  • Stressed eye tolerance testing techniques
  • Closed eye analysis
  • Embedded (or forward) clocking
  • Phase amplitude modulation (PAM) eye and BER analysis
 

10. Leverage High-Speed Signal Processing for Equalization and Coding

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and forward error-correction (FEC) methods. This track covers design, modeling, analysis, and implementation of such techniques.

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithm, modeling and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction)
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • High-speed channel de-embedding and modeling
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Measurement verification
  • Multi-level signaling
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling.
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
 

11. Ensure Power Integrity in Power Distribution Networks

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of supply noise and its impact on overall system performance.

  • Power systems design
    • DC/DC converter design
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management
  • Chip-level power distribution and regulation
    • Charge delivery analysis
    • On-chip regulator, multi-voltage, and power-gating design
  • System-level designs
    • System noise modeling and mitigation
    • Power integrity optimization
    • Chip/package/board power integrity specification and correlation
    • Signal/power integrity co-design
    • Simultaneous switching noise (SSN) suppression
    • Chip/package/board decoupling optimization
  • Jitter analysis and optimization of the power integrity impact
  • Wireless power
  • System level PDN design strategy: PDN performance versus cost, size, yield, reliability, etc.
 

12. Achieve Electromagnetic Compatibility and Mitigate Interference

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

  • EMI radiation and suppression
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Pre-qualification testing for emissions
  • Near-field coupling & crosstalk
  • Noise characterization & containment
  • Emissions & interference modeling
  • Shielding & package design
  • Differential to common-mode conversion
  • EMI measurement: near-field scanning and far-field checks
  • EMI for high-density multi-port systems
  • EMI system susceptibility
  • System radiated and conducted emissions
  • Safety and compliance of power networks
 

13. Apply Test and Measurement Methodology

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

  • Metrology of the measurements
    • Instrumentation performance and measurement errors
    • Resolution & sensitivity
    • Algorithms for accuracy & resolution improvement
    • Calibration & accuracy
  • Methods and system architecture
    • ATE and subsystems
    • Automatic test pattern generation
    • Boundary scan, JTAG & I-JTAG test methods
    • Fluctuations, noise, jitter transformation
  • Active/passive device-measurement methods
    • Analog, mixed signal & RF testing
    • On-die instrumentation
    • SoC testing: memory, IP
    • Package, connector, board testing
    • Testing gigabit I/O
    • Large signal dynamic load response
    • Power supply ripple rejection
  • Fixture de-embedding methodologies
    • Signal integrity and fixture de-embedding
    • 3D-solver and measure-based test fixture design methods
    • Backplane/pin signal integrity
    • Chip/Package/Board/System measurement methods
    • Separation effects of decoupling, power, signal integrity
    • Silicon characterization/de-embedding
    • Probing & on-wafer measurements
  • Advanced measurements & DFM
    • Yield analysis & yield enhancement
    • Fault modeling & failure analysis
    • Prototyping
    • Test coverage
 

14. Ensure Signal Integrity with RF/Microwave/EM Analysis Techniques

Analysis of signals on interconnects with high data rates is evolving to include the extension of techniques originally developed for digital and RF/microwave systems. This track covers signal integrity analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broad-band interconnect systems
  • RF/Microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy)
  • Material parameters identification
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
 

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Review Criteria

The DesignCon 2015 Technical Program Committee is currently conducting its review. All submissions will be reviewed based on quality, relevance, impact, and originality.

A. Quality

DesignCon papers, panels, and tutorials should be well organized and easily understood. The abstract and summary are judged as indicators of what can be expected of the paper or session.

B. Relevance

The proposed paper, panel, or tutorial should be highly relevant to the interests of the DesignCon audience in general and the track topic in particular.

C. Impact

DesignCon papers, panels, and tutorials should contribute to the educational mission of DesignCon. Submissions reporting on important results, methodologies or case studies of special significance will be considered favorably.

D. Originality

Reports on new design methodologies, case studies for innovative designs or other novel results contribute to the DesignCon goal of providing a high-quality educational program for practicing engineers. However, outstanding proposals on "classical" topics will also be viewed favorably.

E. Commercial Content

It is acceptable to use a product in a design case study or as a proof of concept for a design methodology. Product promotion is not permitted in DesignCon technical sessions. Evidence of product promotion in a paper, panel, or tutorial proposal will lead to rejection of the proposal.

All relevant proposals—including topics other than those listed—will be considered. Submissions on related standards activities are welcome.


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