The DesignCon 2016 Call For Abstracts Is Now Closed.

Santa Clara Convention Center, January 19-22 2016


Notifications for acceptance will be sent out by the end of August 2015.
Papers Due for Selected Proposals: November 2, 2015
Slides Due: December 18, 2015

The 2016 Call for Proposals is Now Closed.

Each summer, the DesignCon Technical Program Committee (TPC) issues a Call for Abstracts to the engineering community (typically open May – June). The members of the esteemed TPC then enter into a rigorous review process to carefully select a handful of proposals from the hundreds received in the following months. All applicants are then notified of their submission status between August - September.

Due to this process, we cannot allow any late proposals for our Technical Program. If you missed this year’s deadline, we encourage you to sign- up for our newsletters so you can stay informed of upcoming speaking opportunities. Sign-up here. If you are still interested in exhibiting and other vendor opportunities, including speaking/hosting vendor tech sessions, please contact our .

Check back soon for the full conference schedule!

At DesignCon, engineers talk to engineers to find practical solutions to the challenging problems they share in design and verification. We emphasize education and peer-to-peer sharing among practicing engineers, creating a unique atmosphere for learning about state-of-the-art design methodologies and technologies. Individuals presenting papers at DesignCon will join an elite group offering leading-edge case studies, technology innovations, practical techniques, design tips, and application overviews.

We solicit abstracts for three types of sessions: technical papers, panels, and tutorials. Technical papers, which are up to 25 pages long, address design case studies and application overviews and are presented in 40-minute sessions. Technical panels are 75-minute presentation/discussion sessions featuring 3-5 panelists plus a panel chair to moderate the discussion. Tutorials are 3-hour sessions (papers up to 50 pages long are optional), allowing the speakers to cover topics in greater depth. Tutorials are scheduled for Tuesday, January 19; the technical paper sessions will be held on Wednesday–Thursday, January 20-21; technical panels are scheduled on Tuesday-Thursday at the end of each day’s program.

DesignCon 2016 Tracks

Below is a description of each DesignCon 2016 Track, along with sample topics. All relevant proposals—including topics other than those listed—will be considered.

1. Optimize Chip-Level Designs for Signal/Power Integrity

Chip-level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the on-chip level, from interconnect topologies, transceiver technology and design, to noise and jitter mitigation strategies.

  • Signal integrity (SI), power integrity (PI), and power delivery network (PDN) considerations in chip designs
  • Implications of chip-level decisions on systems design (e.g. frequency, timing, design overhead, voltage)
  • High-speed I/O design
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-gating design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • Clock and reset strategies
  • 2.5D/3D interconnects and interposer design
  • Through-silicon vias (TSV)
  • SIP partition and IP integration
  • On-chip and chip-to-chip interconnect design and analysis
  • Pre-silicon validation and verification
  • Post-silicon validation and verification

2. Analog/Mixed-Signal Modeling & Simulation Challenges

As capabilities expand and complexity grows, today’s chips and systems require new modeling and simulation approaches that ensure design success, but give useful results in a reasonable amount of time. Faster I/Os and waveforms, as well as RF, MEMS, and sensor components require specialized models that take into account analog and high-frequency effects. Yet, mixing these with other models for simulation must be done efficiently to capture critical effects and still give quick answers. This track addresses challenges and solutions for design and verification that may involve various modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability.

  • Statistical eye (StatEye) analysis approaches
  • IBIS-AMI model generation and validation strategies
  • SPICE vs. IBIS modeling and SPICE-to-IBIS
  • Fast SSO simulation and modeling methods.
  • HDL vs. FastSPICE vs. SPICE for AMS
  • Converting Verilog or MATLAB models to IBIS-AMI
  • Fast simulation of package models based on scattering and broadband network parameters
  • Mixed-signal behavioral models for SERDES phase-locked loops
  • Approaches for system-level modeling of nonlinear power amplifiers and I/O buffers
  • Signal, noise, and failure modeling for emerging devices and technologies: e.g. GaN, SiC
  • System reliability prediction and fault-tolerant design with power semiconductors
  • Best practices and tradeoffs between digital Verilog vs. Verilog-AMS
  • Modeling approaches for RF devices for successful system design and integration
  • Successful system design and verification with MEMS accelerometers, CMOS Imaging sensors, or touchscreen technologies
  • Mixed time/frequency analysis approaches
  • Behavioral modeling of clock jitter and phase noise for simulation and verification.
  • How to integrate analog/mixed-signal circuitry into a system design
  • Design solutions for achieving adequate dynamic range, linearity, and sensitivity from audio to RF
  • Simulation of reliability gain/loss by different power topology selection

3. Wireless and Photonic Integration

The aim of this track is to provide a forum covering practices and methodologies used in emerging system designs and applications leveraging wireless and photonic technologies as media for data transmission. There are many challenges in system integration, especially for signal integrity and power integrity. This track looks at what happens when multiple data transmission technologies converge in one design.

  • Techniques to bring together high-speed electrical and high-speed optical circuits
  • Measurement and testing of optical/electrical ICs
  • Dealing with coexistence issues when integrating optical and/or wireless transmission, e.g. EMI, integration
  • Photonic ICs
  • Microwave photonics
  • Photonic interconnects
  • Photonic integration and packaging design
  • Link design
  • Link impairments
  • Electro-optics
  • Optical signal processing
  • Passive components for 100 Gbps/400 Gbps optical communications.
  • Wireless and optical network convergence
  • Layout considerations for RF circuits, photonic circuits
  • Silicon nanophotonics
  • High-speed wireless options
  • Making wireless technology work with digital systems in terms of signal integrity
  • Antenna design and placement
  • FCC qualification; interference mitigation Integrated optical links, optical interconnects
  • Integration of optical subsystems

4. System Co-Design Modeling and Simulation

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • PCB/package/chip/device power modeling
  • Interaction of protection devices
  • End-to-end link modeling
  • Pin-out optimization, signal fan-out
  • First- and second-level interconnect analysis
  • Sub-system interaction
  • System-level power and signal integrity
  • Buffer modeling
  • High-speed signaling
  • I/O interoperability
  • Merging of chip design and package design
  • Mixed-signal system design
  • Multi-voltage design
  • Package modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP) design
  • 3D/2.5D on-chip interconnect design and analysis
  • Performance trade-offs: electrical, mechanical, thermal

5. Characterize PCB Materials & Processing

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

  • Advanced conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Microvias, RF vias and thermal vias
    • High aspect-ratio vias
    • What materials should I choose?
  • Advanced laminate and PCB processing
    • Interlayer connectivity alternatives
    • Fine registration improvements
    • Backdrilling methods and effects
  • Embedded devices
    • Passive and active devices
    • Embedded optical channels
    • Power delivery
  • 40-Gbps PHY channel development and characterization
  • Rigid-flex and multilayer flex circuit design and manufacturing
  • Lead-free materials (RoHS)
  • Fabrication: cost ,performance, reliability trade offs
  • Manufacturing impact on electrical properties
  • Determining material properties
  • Glass weave effects on signal quality
  • Materials characterization and modeling
  • Optical waveguides
  • PCB and package considerations
  • PCB materials for high-speed power integrity
  • Sockets and connectors
  • Reducing the Q of PCB planes
  • Thermal characterization

6. Apply PCB Design Tools

High-speed data transfer and telecommunications are supported by PCB platforms that typically constitute more than 80% of the channel length while concurrently supporting power delivery, mixed-signal requirements and advanced serial data speeds. This track explores effective high-speed design and design choices using a wide range of E-M modeling techniques, PCB characterization tools, and test platforms to optimize PCB platforms such as backplanes, mid-planes, and daughter cards combined with separable interconnects and optical channels.

  • 40-Gbps PHY channel development and characterization
  • Electrical, optical, and mechanical co-design: choices and trade offs
  • How to simulate PI and SI on a PCB
  • EM modeling of PCB traces and vias
  • PCB design challenges, tools, and techniques
  • PCB test and measurement
  • Board layout techniques for power and signal integrity
  • Thermal and noise interaction between digital interfaces and subsystems
  • Sockets and connectors
  • Via pin-field design
  • Case studies (caution: must be non-commercial)
  • Design challenges for wearable electronics
    • Material/dielectric modeling and characterization
    • Simulation accounting for change in material e.g., when flexed or bent
  • Advances in high-speed conductive surface modeling
    • EM toolsets and EDA support
    • Copper roughness
    • Characterization

7. Design Memory and Parallel Interfaces

Memory and parallel interface designs continue to be challenged with complex performance requirements including bandwidth, power consumptions, and form factors. This track addresses the latest design techniques and signal and power integrity issues to meet these performance requirements for various chip-to-chip interfaces. I/O system used in 2.5D, 3D, on-chip, SiP, and MCM are covered in this track in addition to conventional PCB interface designs.

  • Memory interface and 3D integration
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
    • WideIO, HBM, and HMC memory interfaces
    • Proprietary or emerging 2.5D and 3D I/O interfaces
  • High-speed parallel interface design
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2)
    • Clocking architecture
    • Parallel interconnect signal conditioning techniques
    • Low-power designs
  • Signal integrity simulation
    • Supply noise induced jitter modeling
    • Crosstalk and simultaneous switching noise impacts
    • Differential vs single-ended signaling
    • Statistical timing models including jitter amplification, tracking, bit error rate analysis
    • Power, thermal cost versus performance analysis

8. Optimize High-Speed Serial Design

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

  • Backplane and cable interconnect
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Loss and timing budgets for electrical or optical links
  • Physical modeling and simulation
  • Signal integrity for backplanes and cables
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • PAM-4 vs NRZ system trade-offs/case studies
  • WDM in backplane

9. Detect and Mitigate Jitter, Crosstalk, and Noise

Whether or not a system operates at the required bit error rate (BER) is the fundamental measure of signal integrity. This track concentrates on the causes of errors, including, but not limited to jitter, crosstalk, and noise, and techniques for measuring and estimating BER performance such as total jitter, eye height, and BER contour.

  • Bit error rate (BER), signal-to-noise, and distortion analysis and measurement
  • Measurement and estimation of total jitter, eye opening, and eye height defined at a BER
    • Jitter simulation, analysis, and measurement
    • Jitter modeling techniques (stochastic/ deterministic, correlated/uncorrelated)
  • Jitter, noise, and BER/FER analysis of PAM-4 signals
  • Relationship between S-parameters and errors
  • Dispersion and inter-symbol interference analysis and compensation
  • Bounded uncorrelated jitter (BUJ) and crosstalk analysis, mitigation, and effect on BER.
  • Noise analysis for diagnostics and compliance
  • Time/frequency domain, phase noise, and jitter spectrum analysis and prediction
  • Stressed eye tolerance testing techniques
  • Closed eye analysis
  • Embedded (or forward) clocking
  • BER/FER analysis in the presence of FEC

10. High-Speed Signal Processing for Equalization & Coding

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and forward error-correction (FEC) methods. This track covers design, modeling, analysis, and implementation of such techniques.

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithm, modeling and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction)
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • High-speed channel de-embedding and modeling
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Measurement verification
  • Multi-level signaling
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling.
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
  • Back-channel training methods and performance

11. Power Integrity in Power Distribution Networks

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of supply noise and its impact on overall system performance.

  • System level PDN design strategy
    • PDN performance versus cost, size, yield, reliability, etc.
    • PDN specifications
    • System noise modeling and mitigation
    • Supply noise induced jitter analysis and optimization
  • Power Integrity in system-level designs
    • Chip/package/board system power integrity research
    • Simultaneous switching noise (SSN) suppression
    • Chip/package/board decoupling optimization
    • Signal/power integrity co-design
    • Measurements and correlation
  • Chip-level power distribution and regulation
    • Dynamic and static voltage variations
    • Charge delivery analysis
    • On-chip regulator, multi-voltage, and power-gating design
  • Power supply design
    • DC/DC converter and VRM design
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management
    • Wireless power

12. Electromagnetic Compatibility/Mitigating Interference

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

  • EMI radiation and suppression
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Pre-qualification testing for emissions
  • Near-field coupling and crosstalk
  • Noise characterization and containment
  • Emissions and interference modeling
  • Shielding and package design
  • EMI measurement: near-field scanning and far-field checks
  • EMI for high-density multi-port systems
  • EMI system susceptibility

13. Apply Test and Measurement Methodology

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

  • Methods and practices of measurements
    • Instrumentation performance and measurement errors
    • Resolution and sensitivity
    • Algorithms for accuracy and resolution improvement
    • Calibration and accuracy
  • Standards-based measurement methods
    • PAM-4, PAM-2, Ethernet, DDR, etc.
    • S-Parameter quality
    • Causality and passivity of measurements
  • Active/passive device-measurement methods
    • Analog, mixed-signal and RF testing
    • On-die instrumentation
    • SoC testing: memory, IP
    • Package, connector, board testing
    • Testing gigabit I/O
    • Large signal dynamic load response
    • Power supply ripple rejection
  • Fixture de-embedding methodologies
    • Signal integrity and fixture de-embedding
    • 3D-solver and measure-based test fixture design methods
    • Backplane/pin signal integrity
    • Chip/package/board/system measurement methods
    • Separation effects of decoupling, power, signal integrity
    • Silicon characterization/de-embedding
    • Probing and on-wafer measurements
  • Methods and system architecture
    • ATE and subsystems
    • Automatic test pattern generation
    • Boundary scan, JTAG and I-JTAG test methods
    • Fluctuations, noise, jitter transformation
    • Yield analysis and yield enhancement
    • Fault monitoring and failure analysis

14. Signal Integrity with RF/EM Analysis Techniques

Analysis of signals on interconnects with high data rates often includes the extension of techniques originally developed for digital and RF/microwave systems. This track covers signal integrity analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • RF/microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • Material parameters identification
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)

The Call for Proposals is Now Closed
If you have any questions about the CFA process, please feel free to reach out to Janine Love .

For more information about attending DesignCon 2016, visit: