• Conference
    Jan 31-Feb 2, 2017
  • Expo
    Feb 1-2, 2017
  • Santa Clara, CA
    Santa Clara Convention Center

2017 CALL FOR ABSTRACTS

TECHNICAL PAPERS, PANELS AND TUTORIALS

Santa Clara Convention Center, January 31, 2017 – February 2, 2017

Deadline for Abstracts: August 16, 2016 
Papers Due: November 15, 2016

We are pleased to announce this Call for Technical Papers, Panels and Tutorials for DesignCon 2017, the premier educational conference and technology exhibition for semiconductor and electronic design engineers. At DesignCon, engineers talk to engineers to find practical solutions to the challenging problems they share in design and verification. We emphasize education and peer-to-peer sharing among practicing engineers, creating a unique atmosphere for learning about state-of-the-art design methodologies and technologies. Individuals presenting papers at DesignCon will join an elite group offering leading-edge case studies, technology innovations, practical techniques, design tips, and application overviews.

We solicit abstracts for three types of sessions: technical papers, panels, and tutorials. Technical papers, which are up to 25 pages long, address design case studies and application overviews and are presented in 40-minute sessions. Technical panels are 75-minute presentation/discussion sessions featuring 3-5 panelists plus a panel chair to moderate the discussion. Tutorials are 3-hour sessions (papers up to 50 pages long are optional), allowing the speakers to cover topics in greater depth. Tutorials are scheduled for Tuesday, January 31; the technical paper sessions will be held on Wednesday–Thursday, February 1-2; technical panels are scheduled on Tuesday-Thursday at the end of each day’s program.

To Submit a Proposal

Prepare the following information and submit ONLINE by August 16, 2016:

  • Title of submission
  • Conference track preference (required), secondary track preference (optional). (Reviewers may move your submission to a more appropriate track based on the content provided in the submission)
  • Session format: 40-minute technical paper, 75-minute panel discussion, or 3-hour tutorial (If you have a secondary format preference, please note in the comments)
  • Audience level (all or advanced, REQUIRED) – prerequisites required for advanced
  • Key takeaways (50 words max, REQUIRED) – for use in the review process
  • Abstract (100 words max, REQUIRED) – for use on conference web site and mobile app if accepted
  • Extended abstract (500 words max, REQUIRED) – for use by reviewers to judge your proposal
  • Prerequisites (50 words max) – required for advanced audience levels
  • Keywords: Select relevant keywords
  • Comments (optional) – additional information for reviewers and staff in their consideration of your proposal
  • Authors can upload supplemental documents to support their proposal (optional)

Review Criteria

The DesignCon 2017 Technical Program Committee reviews all submissions based on quality, relevance, impact, and originality. Prospective authors are welcome to reference products as long as product references add to the educational value and are presented in an appropriately non-commercial fashion.

A. Quality – DesignCon papers, panels, and tutorials should be well organized and easily understood. The abstract and summary are judged as indicators of what can be expected of the paper or session.
B. Relevance – The proposed paper, panel, or tutorial should be highly relevant to the interests of the DesignCon audience in general and the track topic in particular.
C. Impact – DesignCon papers, panels, and tutorials should contribute to the educational mission of DesignCon. Submissions reporting on important results, methodologies, or case studies of special significance will be considered favorably. Submissions on related standards activities are welcome.
D. Originality – Reports on new design methodologies, case studies for innovative designs, or other novel results contribute to the DesignCon goal of providing a high-quality educational program for practicing engineers. However, outstanding proposals on “classic” or “introductory” topics will also be viewed favorably.
E. Commercial contentProduct promotion is not permitted in DesignCon technical sessions. Evidence of product promotion in a paper, panel, or tutorial proposal will lead to rejection of the proposal. It is acceptable to use a product in a design case study or as a proof of concept for a design methodology.

Note: The DesignCon Technical Program Committee reserves the right to request edits to submitted papers, or to reject a submitted paper if it fails to match the accepted abstract or above guidelines.

DesignCon 2017 Tracks

Below is a description of each DesignCon 2017 Track, along with sample topics. All relevant proposals—including topics other than those listed—will be considered.

Chip and package level decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at the chip & package level, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Sample Topics

  • Signal integrity (SI), power integrity (PI), and power delivery network (PDN) considerations in chip designs
  • Implications of chip-level decisions on systems design (e.g. frequency, timing, design overhead, voltage)
  • High-speed I/O design
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-gating design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • Clock and reset strategies
  • 2.5D/3D interconnects and interposer design
  • Through-silicon vias (TSV)
  • SIP partition and IP integration
  • On-chip and chip-to-chip interconnect design and analysis
  • Pre-silicon validation and verification
  • Post-silicon validation and verification

Today’s chips and systems require new modeling and simulation approaches that have adequate accuracy to ensure design success, but give useful results quickly. Faster data channels and interfaces require specialized models that take into account analog and high-frequency effects. Yet, combining these with behavioral models (such as IBIS-AMI) for fast simulation must be done carefully to capture critical eye effects. This track addresses challenges and solutions for design and verification that may involve various modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability.

Sample Topics:

  • Statistical eye (StatEye) analysis approaches
  • IBIS-AMI model generation and validation strategies
  • SPICE vs. IBIS modeling and SPICE-to-IBIS
  • Fast SSO simulation and modeling methods.
  • HDL vs. FastSPICE vs. SPICE for AMS
  • Converting Verilog or MATLAB models to IBIS-AMI
  • Fast simulation of package models based on scattering and broadband network parameters
  • Mixed-signal behavioral models for SERDES phase-locked loops
  • Approaches for system-level modeling of nonlinear power amplifiers and I/O buffers
  • Signal, noise, and failure modeling for emerging devices and technologies: e.g. GaN, SiC
  • System reliability prediction and fault-tolerant design with power semiconductors
  • Best practices and tradeoffs between digital Verilog vs. Verilog-AMS
  • Modeling approaches for RF devices for successful system design and integration
  • Successful system design and verification with MEMS accelerometers, CMOS Imaging sensors, or touchscreen technologies
  • Mixed time/frequency analysis approaches
  • Behavioral modeling of clock jitter and phase noise for simulation and verification.
  • Simulation of reliability gain/loss by different power topology selection

Integrating photonics into electrical design presents unique technical and practical challenges to meet high data rate requirements. PAM4 and other modulation schemes, coupled with high channel losses and nonlinear optics, demand complex equalization, re-timers and integration of FEC within the receiver. While the technical challenges are formidable, the practical power and thermal issues arising due to high density and smaller size requirements must be addressed, and will be covered in this track.

Sample Topics

  • Techniques to bring together high-speed electrical and high-speed optical circuits
  • Measurement and testing of optical/electrical ICs
  • Dealing with coexistence issues when integrating optical and/or wireless transmission, e.g. EMI, integration
  • Photonic ICs
  • Microwave photonics
  • Photonic interconnects
  • Photonic integration and packaging design
  • Link design
  • Link impairments
  • Electro-optics
  • Optical signal processing
  • Passive components for 100 Gbps/400 Gbps optical communications.
  • Wireless and optical network convergence
  • Layout considerations for RF circuits, photonic circuits
  • Silicon nanophotonics
  • High-speed wireless options
  • FCC qualification; interference mitigation Integrated optical links, optical interconnects
  • Integration of optical subsystems

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

Sample topics

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • PCB/package/chip/device power modeling
  • Interaction of protection devices
  • End-to-end link modeling
  • New technology design, including IoT design and 5G system co-design
  • First- and second-level interconnect analysis
  • Sub-system interaction
  • System-level power and signal integrity
  • Buffer modeling for system simulation
  • System co-design for high-speed signaling
  • I/O interoperability
  • Merging of chip design and package design
  • Mixed-signal system design
  • Multi-voltage design
  • Package modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP) design
  • 3D/2.5D on-chip interconnect design and analysis
  • Performance trade-offs: electrical, mechanical, thermal

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

Sample topics

  • Advanced conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Microvias, RF vias and thermal vias
    • High aspect-ratio vias
    • What materials should I choose?
  • Advanced laminate and PCB processing
    • Interlayer connectivity alternatives
    • Fine registration improvements
    • Backdrilling methods and effects
  • Embedded devices
    • Passive and active devices
    • Embedded optical channels
    • Power delivery
  • Rigid-flex and multilayer flex circuit design and manufacturing
  • Lead-free materials (RoHS)
  • Glass weave effects on signal quality
  • Materials characterization and modeling
  • Optical waveguides
  • Sockets and connectors
  • Thermal characterization
  • Creative ways to eliminate skew in very high-speed differential paths
  • Advances in low loss laminates
  • Advances in copper surfaces
  • Advances in thin dielectrics

High-speed data transfer up to 56-Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112-Gbps? Can PCB support high current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization tools, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

Sample topics

  • 40-GHz PHY channel development and characterization
  • Electrical, optical, and mechanical co-design: choices and trade offs
  • How to simulate PI and SI on a PCB
  • EM modeling of PCB traces and vias
  • PCB design challenges, tools, and techniques
  • Board layout techniques for power and signal integrity
  • Thermal and noise interaction between digital interfaces and subsystems
  • DC power supply and PCB co-simulations
  • Sockets and connectors
  • Via pin-field design
  • Case studies (caution: must be non-commercial)
  • Design challenges for wearable electronics
    • Material/dielectric modeling and characterization
    • Simulation accounting for change in material e.g., when flexed or bent
  • Advances in high-speed conductive surface modeling
    • EM toolsets and EDA support
    • Copper roughness
    • Characterization

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in IO interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, and form factor. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various IO interfaces.

Sample Topics

  • 2.5D/3D/SiP interface
    • HBM, HMC and WideIO interfaces
    • Proprietary or emerging 2.5D/3D/SiP IO interfaces
  • Memory interface
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
  • High-speed parallel interface
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2)
    • Parallel interconnect signal conditioning techniques
    • Low-power designs
  • Signal/power integrity simulation
    • Supply noise induced clock and data jitter analysis
    • Channel crosstalk, simultaneous switching noise, and statistical timing models

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

Sample topics

  • Backplane and cable interconnect
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Loss and timing budgets for electrical or optical links
  • Physical modeling and simulation
  • Signal integrity for backplanes and cables
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • PAM-4 vs NRZ system trade-offs/case studies
  • WDM in backplane

The impact of Jitter, Noise, Crosstalk, ISI, and reflection have a detrimental impact on BER. Simulation, measurements, and analysis techniques that improve the insight and analysis of these factors to minimize system BER performance will be presented in this track.

Sample topics

  • Bit error ratio (BER), signal-to-noise ratio (SNR), and distortion analysis and measurement
  • Measurement and estimation of total jitter, eye width, and eye height defined at a BER
  • Jitter simulation, analysis, and measurement
    • Jitter modeling techniques (stochastic/ deterministic, correlated/uncorrelated)
    • Jitter, noise, and BER/frame error ratio (FER) analysis of PAM-4 signals
  • Relationship between S-parameters and errors
  • Dispersion and inter-symbol interference (ISI) analysis and compensation
  • Bounded uncorrelated jitter (BUJ) and crosstalk analysis, mitigation, and effect on BER.
  • Noise analysis for diagnostics and compliance
  • Time/frequency domain, phase noise, and jitter spectrum analysis and prediction
  • Stressed eye interference tolerance testing techniques
  • Closed eye analysis
  • Embedded (or forward) clocking and related jitter mitigation techniques
  • BER/FER analysis in the presence of forward error correction (FEC)

High-speed communication systems require increasingly complex signal-processing techniques; including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Sample topics

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithms, modeling and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction)
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • High-speed channel de-embedding and modeling
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Measurement verification
  • Multi-level signaling
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling.
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
  • Back-channel training methods and performance

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

Sample topics

  • System level PDN design strategy
    • PDN performance versus cost, size, yield, reliability, etc.
    • PDN specifications
    • System noise modeling and mitigation
    • Supply noise induced jitter analysis and optimization
  • Power Integrity in system-level designs
    • Chip/package/board system power integrity research
    • Simultaneous switching noise (SSN) suppression
    • Chip/package/board decoupling optimization
    • Signal/power integrity co-design
    • Measurements and correlation
  • Chip-level power distribution and regulation
    • Dynamic and static voltage variations
    • Charge delivery analysis
    • On-chip regulator, multi-voltage, and power-gating design
  • Power supply design
    • DC/DC converter and VRM design including state-of-the art GaN technology
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management
    • Wireless power

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

Sample topics

  • Design techniques to reduce or eliminate sources of EMI
  • EMI radiation and suppression
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Pre-qualification testing for emissions
  • Near-field coupling and crosstalk
  • Noise characterization and containment
  • Emissions and interference modeling
  • Shielding and package design
  • EMI measurement: near-field scanning and far-field correlation
  • EMI for high-density multi-port systems
  • EMI system susceptibility

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Sample topics

  • Measurement methodologies for Signal Integrity, Power Integrity, and EMI/EMC
  • Standards-based measurement methods for PAM-4, Ethernet, PCIe, USB, DDR, etc.
  • S-Parameter quality, causality, and passivity of measurement calibration methods
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Passive device-measurement methods for on-die, package, connector, board testing
  • Power supply noise measurement methods for dynamic load response, ripple injection…
  • Signal integrity of fixture design for PCB, connectors, package, on-die, measurements.
  • Fixture de-embedding techniques including EM-solver and measure based models
  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
  • Measurement methods and instrumentation architecture
  • ATE and sub-systems design validation and production at speed testing

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

Sample topics

  • Signal integrity analysis with RF/Microwave techniques
  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • RF/microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • Dielectric, conductor and conductor roughness model parameters identification
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpintines)

Deadline for Abstracts: August 16, 2016