With Design and Test for Multiple Gbps Communication Devices and Systems in hand, you will learn and master the basics of today's design and test methodologies and techniques. With this enhanced knowledge, you will be able to more fully understand the current challenges facing today's practitioners, as well as which existing solutions are best to combat those challenges.

This will help you to choose the right methods and tools for your designs and tests and will enable you to achieve greater efficiency, higher performance, and higher yields. This will ultimately lead to fewer device respins, faster times to market, on-time delivery, and higher overall productivity.

This collection of acclaimed papers from leading experts in industry and academia maintains a good balance between theory foundation and practical applications, with a strong emphasis on signal integrity and jitter, while presenting the latest technologies, methodologies, and advancements in design and test for multiple Gbps devices and systems.

The Functional Verification of Electronic Systems offers a comprehensive overview of functional verification from the points of view of leading experts currently at work in the electronic-design industry. As the size and complexity of modern chip designs have increased, the need for full and accurate functional verification during the design process has become still greater. Many companies are now realizing that verification is something they need as a core competence. However, the process of verification can devour a large portion of the effort devoted to a design project.

To address this, various techniques have emerged with the aim of improving the efficiency and effectiveness of the verification process. These include coverage, simulation, testbench automation, transaction-level modeling, and assertion-based verification. The Functional Verification of Electronic Systems examines past and current verification landscapes and assesses the technologies, languages, and methodologies in use today that will improve functional verification into the future.

DesignCon 2006
February 6 – 9, 2006
Santa Clara Convention Center, Santa Clara, California, USA