More details on Training Boot Camps – limited spots available! Get your pass today.

  • Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center 
    | Santa Clara, CA

ANSYS’ new Chip-Package-System (CPS) design flow delivers unparalleled simulation capacity and speed for power integrity, signal integrity EMI, ESD and thermal stress challenges. ANSYS’ unique layout assembly capability integrates IC package layout, interposers, connectors, ribbon cables, flex cables, and PCB all within a single assembly. This facilitates the emerging CPS design process to support new and existing electronic devices. Automated thermal analysis and integrated structural analysis capabilities provide coupled chip-aware and system-aware simulation for CPS design enabling customers to perform end-to-end multiphysics analysis.