By Barry Sullivan DesignCon Program Director

The IP Summit

You may have noticed that we will feature the IP Summit at DesignCon 2009. So what is this IP Summit and why is it part of DesignCon? The "what" I can answer directly: a "conference within the conference" addressing the role of semiconductor IP in electronic design, fully integrated with the DesignCon program, including featured speakers, panels, tutorials, technical papers, and exhibits.

As for why, I’ll explain it the way I did to Chiphead. I felt it was something I had to run by him first. As always when the topic turns to DesignCon, Chiphead was quietly attentive.

Read more...

IEC Publications Preview

Intellectual Property for Electronic Systems: An Essential Introduction Special DesignCon Newsletter Price: USD $60 List Price: USD $80 Discount Code: DCNEWS1 Order Today!

Executive Editors:
Brian Bailey, Proprietor, Brian Bailey Consluting
Kathy Werner, IP Strategy and Business Manager, Freescale Semiconductor, President, VSI Alliance

Chapter 10: IP Selection

Chapter Authors:
Adam Traidman, President, Chip Estimate Corporation
Pallab Chatterjee, Chief Technical Officer,
SiliconMap, LLC

If intellectual property (IP) were like other electronics components, such as computer parts, one would simply visit the local IP retailer, peruse the shelves, perhaps consult an online review site, and then purchase the selected IP. Install would be easy, solely consisting of “plug-and-play” and one would be ready to go. Unfortunately, the world of IP, as it stands today, does not yet address this ideal scenario.

Read full chapter…

Design and Application of Embedded Waveform Viewing Technology for Integrated Circuits

Company: Vitesse Semiconductor Corporation
Gary McCormack, Eric Sweetman, and Ian Kyles

Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended SignalingSchemes

Company: Rambus Inc.
Dan Oh, Woopoung Kim, Joong-Ho Kim, John Wilson, Ralf Schmitt, Chuck Yuan, Lei Luo, Jade Kizer, John Eble, and Fred Ware

Mode Conversion and EMI Performance of Shielded Cable Assemblies for 10 Gbps Data Transmission

Company: Samtec
Jim Nadolny, Julian Ferry, and Cesar Arroyo

Exhibit space is selling quickly!
Book your space today!

Each year, the semiconductor and electronic design engineering communities look forward to DesignCon for showcasing the latest technologies and developments in their industry.

Exhibitor Prospectus
Exhibit Floor Plan
View exhibitor list

Contact:
Christine Paplaczyk
Exhibit Sales Director
DesignCon 2008
Phone: +1-312-559-4616
E-mail: cpaplaczyk@iec.org

Rob Aitken Fellow Arm Holdings PLC

Alexander Shubat, Ph. D. Chief Operating Officer Virage Logic

I am an IP Chiphead

Adam Traidman Group Marketing Director, Chip Planning Solutions Cadence Design Solutions

“We view DesignCon as a highly tuned conduit to Silicon Valley design teams who are interested in taking advantage of new products and services to accelerate their business,” said Adam Traidman, former president and CEO of Chip Estimate Corporation. “In addition to launching ChipEstimate.com at the show several years past, the event has also played an important role in helping to fuel brand awareness and growth in our community of users.”

Download a copy of the DesignCon 2009 Conference Brochure for complete details of this definitive event for electronic design engineers.

Early Reg cut off is December 19th...

Register by December 19 to receive your free Exhibits PLUS ChipHead Pass or discount on all conference registrations.

Register Today!

Promotion code: Chiphead18

Hotel cut-off date is fast approaching:

On-line: Book Your Room
Phone: +1-408-200-1234
Directions

Chiphead Video Contest Extended!

Due to popular demand the cut-off date has been extended to January 5, 2009

Enter for a chance to win the $2,500 1st Place Prize!

The Assignment: Create a video that is a minimum of 1 minute, and a maximum of 5 minutes…

See full contest rules

Chiphead's Top Picks- On The Road to DesignCon 2009... The IP Summit

IP Summit Chair and
Monday Keynote Luncheon Speaker

Mark Gogolewski Chief Technology Officer Denali Software

View Mark Gogolewski's interview

1:30 pm - 4:30 pm
CoReUse/QCore – Industries First Design Reuse Methodology with Compliance Checking Tool

Technical Paper Sessions – Track 3,
IP Re-Use and Integration

8:30 am – 9:10 am
Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP

9:20 am – 10:00 am
Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design Reusability

10:15 am - 10:55 am
Intellectual Property – Fraud Protection

10:15 am - 11:45 am
Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers

11:05 am - 11:45 am
Toward Harnessing the True Potential of IP Reuse

2:00 pm - 2:40 pm
C++IP Design and Reuse

2:50 pm - 3:30 pm
Skeleton, an Approach to Maximize Reuse across Multiple Product Families

3:45 pm - 5:00 pm
Selecting IP in a Complex Design Environment

Join the DesignCon 2009 Chipheads Group on LinkedIn!

Getting everyone together for a “meet and greet” throughout the year is challenging to say the least, so head over to the Santa Clara Convention Center once a year for the annual DesignCon event and stay in contact with your fellow Chipheads throughout the rest of the year on LinkedIn! Discuss the latest topics in electronic design, give a preview of your booth, or contact colleagues and panel speakers to plan your DesignCon 2009 experience.

Join the DesignCon 2009 Chipheads group today!

DesignCon 2009 Associate Sponsor GSA is conducting a supply chain ecosystem survey that will highlight the obstacles companies are facing in the semiconductor industry. Give us your feedback and support GSA’s mission to be a platform for industry collaboration.

Be a solutions driver: Tell us which topics you feel are most important and need the most improvement in:

EDA/Design

IP

Wafer Manufacturing

Packaging

Test

Take the Survey

Look for a snapshot of the findings in the
January 2009 Newsletter!