• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    | Santa Clara, CA

Keysight Education Forum

DAY 1 - Wednesday, February 1

This session offers SI engineers and their managers a chance to review many of the concepts required for highly-accurate SERDES link simulations, and achieving close correlation to measurement. The session will begin with S-parameter basics, how to tell if you have a high-quality S-parameter model for the purposes of SERDES link simulations. Next up, how the simulation works, avoiding common pitfalls and what simulation trade-offs you have at your fingertips. Followed by an overview of what IBIS-AMI is, and how the designer can more effectively exercise the models. Finally, we conclude with tips for improving measurement accuracy and lowering uncertainty when comparing measured data to simulation data.

Stephen Slater

With PCI Express devices supporting speeds of up to 16GBits per second, many new challenges arise in the area of signal integrity, transmitter signal quality, channel characterization and especially receiver sensitivity testing. In this session, we'll bring you up to speed on the tools and techniques you can use to be successful with your PCI Express 4.0 devices and specifically what you'll need to prepare for to test the physical layer, Gen4 requirements for your transmitter and receiver. 

Rick Eads
Pegah Alavi

The USB Type-C Gen1 (5 Gbps) and Gen2 (10 Gbps) channels are some of the more challenging architectures for digital design engineers due to the extreme rise-time of transitions between zeros and ones. The small physical size of this high density reversible connector increases the risk that design engineers will encounter unforeseen interoperability issues due to the physical layer. These problems can be avoided by leveraging measurements and simulations to adequately debug and characterize the performance driving interconnect features and fabrication tolerances. There are also unexpected power integrity challenges with the new 100 Watts of power delivery that must be dealt with in a logical manner. This seminar will show a step-by-step process that can be implemented by signal integrity engineers to assure their success designing with a high speed serial bus.

Heidi Barnes
Mike Resso

PAM-4 technology is advancing from simulation to the arrival of the first prototype hardware into the lab. Engineers are now facing the task of characterizing their design and testing for pre-compliance to 400G Ethernet or OIF CEI-56G standards which are still under development. Links using PAM-4 signaling are susceptible to impairments not of concern in conventional NRZ signaling. To assure reliable operation, the standards have added new transmitter output measurements as well as different stressed input testing for receivers. This session covers both electrical and optical input testing to compliance of the latest drafts of these standards, as well as additional tests for design validation to assure interoperability.

Steve Sekel

Day 2 - Thursday, February 2

The revolutionary switch to PAM-4 signaling used in 400G Ethernet (IEEE 802.3bs), OIF CEI-56G, and other standards introduces many new design and test challenges. Even though the Standards are still under development, engineers are already being tasked with characterizing new optical and electrical designs based on PAM-4 technology. Attend this session to learn about updates to new measurements performed on electrical and optical PAM-4 transmitters, and discover new tools that will help you characterize and debug your 400G designs quickly and accurately.

Rob Sleigh
Greg LeCheminant

The USB Type-C ecosystem includes technologies like USB 3.1 Gen 2, USB-PD, MHL, Thunderbolt 3, DisplayPort, and HDMI Alt Mode.

As the USB Type-C ecosystem moves into the main-stream with world-wide adoption, there are significant learnings from early silicon and system implementations. This session will illustrate the most common challenges implementing USB Type-C, and solutions to properly characterize and validate your designs.

Jit Lim

Signal integrity and power integrity issues are often the root cause when systems don't behave as expected. Learn new techniques to gain rapid insight into power integrity and signal integrity in systems with high speed DDR4/LPDDR4 memory.

Observe how to easily acquire cross-correlated measurements of traffic on DDR/LPDDR buses and the power integrity of systems. Innovative new probing of power usage and supply voltage fluctuations are used to correlate power usage and power integrity to specific areas of memory activity.

Access to DDR4 and LPDDR4 memory signals for signal integrity characterization is beyond challenging. Observe unique time saving bus level signal integrity insight and understand how to use this insight to debug high speed memory systems.

Key Takeaways:

  • Successful probing and measurement correlation techniques
  • Correlation of system power integrity and signal flow of DDR/LPDDR memory
  • Bus Level Signal Integrity Insight overview and examples.

Jennie Grosslight
Kenny Johnson

R&D designers perform measurements to conclude if their designs meet pass limits set by the high speed Standard committee or the company's standard design guidelines. This webcast will discuss how Keysight's new Data Analytics software capability addresses the needs of designers and their managers to be able to analyze their test results more quickly and in an intuitive manner. Attendees will learn how Keysight's Data Analytics software will enable them to make faster decisions and reduce time to market of their products.

Brad Doerr
Brig Asay