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What’s New in the Server Environment of Power ISA v2.06? Satish Kumar Sadasivam, Staff Software Engineer,IBM Prathiba Kumar, System Software Engineer,IBM Varun Mallikarjunan, Software Engineer,IBM Sponsored by: Power.org	DesignCon 2010
Chip-Package-Board Design Needs for SI/PI: The CAD Perspective within the IC Industry Souvik Mukherjee, CAD/Methodology Engineer,Texas Instruments Sponsored by: Apache Design Solutions	DesignCon 2010
Logic Core PDN Performance in the 30MHz and 1GHz Bands Larry Smith, Principal Engineer,Altera Corporation Peter Boyle, Manager,Altera Corporation Shishuang Sun, Senior Engineer,Altera Corporation Sponsored by: Apache Design Solutions	DesignCon 2010
Chip-Package-System Noise Integrity Aveek Sarkar, Vice President of Product Engineering and Customer Support,Apache Design Solutions Sponsored by: Apache Design Solutions	DesignCon 2010
Introduction to System-Level Power Integrity Analysis: Broadcom Network Switch Jim Antonelis, Principal Engineer,Broadcom Corporation Sponsored by: Apache Design Solutions	DesignCon 2010

Creating C++ IP for High Performance Hardware Implementations of FFTs Andres Takach, Chief Scientist, Mentor Graphics	DesignCon 2010
Strong Encryption and Correct Design Are Not Enough: Protecting Your Secure System from Side Channel Attacks Luke Teyssier, Senior Staff Engineer, Cryptography Research, Inc.	DesignCon 2010
SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity Myoung Joon Choi, Senior Analog Engineer, Intel Vishram Pandit, Senior Analog Design Engineer, Intel Ashish N. Pardiwala, Analog Design Engineer, Intel Hsiao-ching Chuang, Analog Circuit Engineer, Intel Md. Ruhul Quddus, Power Integrity Engineer, Intel	DesignCon 2009
Feasibility Study of a 3.2Gb/s Memory Interface in Ultra Low-Cost LQFP Packages Ralf Schmitt, Signal Integrity Engineer, Rambus Inc. Chuck Yuan, Signal Integrity Manager, Rambus Inc. Joong-Ho Kim, Senior Member of Technical Staff, Rambus Inc. Dan Oh, Engineering Manager, Rambus Inc. June Feng, Senior Member of Technical Staff, Rambus Inc. Ming Li, Packaging Engineer, Rambus Inc. Arun Vaidyanath, Engineering Manager, Rambus Inc. Wendem T. Beyene, Senior Principal Engineer, Rambus Inc.	DesignCon 2009
Worst Case Switching Pattern for Core Noise Analysis Aveek Sarkar, Vice President of Product Engineering and Customer Support, Apache Design Solutions Shen Lin, Chief Technology Officer, Apache Design Solutions Ji Zheng, Director of Engineering, Apache Design Solutions Wheling Cheng, Team Leader, Cisco Systems	DesignCon 2009
Design Space Exploration for high performance signal processing hardware using ESL design methodologies Nitin Chawla, Member of Technical Staff, STMicroelectronics Pascal Urard, High-Level Synthesis Manager, STMicroelectronics Harvinder Singh, Technical Specialist, STMicroelectronics Gagan Midha, Senior Design Engineer, STMicroelectronics Pierre Busson, Advanced Architect Expert, STMicroelectronics Thierry Michel, DSP Architect, STMicroelectronics	DesignCon 2009
A Simple Via Experiment Michael Steinberger, Distinguished Member of Technical Staff, SiSoft Chong Ding, Signal Integrity Engineer, Cisco Systems Divya Gopinath, Intern, Cisco Systems Stephen Scearce, Manager, Cisco Systems Doug White, Technical Leader, Cisco Systems	DesignCon 2009
Towards Harnessing the True Potential of IP Reuse C. Norris Ip, Senior Architect, Jasper Design Automation Rajeev Ranjan, Chief Technology Officer, Jasper Design Automation Craig Deaton, Principal Engineer, Jasper Design Automation Lawrence Loh, Director of World-wide Applications Engineering, Jasper Design Automation Homayoon Akhiani, Principal Engineer, Jasper Design Automation Yann Antonioli, Product Manager, Jasper Design Automation	DesignCon 2009
Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP Mick Posner, Product Manager, Synopsys	DesignCon 2009
Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design Re-Usability Lior Amarilio, Chief Architect, ChipX Ran Rosenzweig, Mixed-Signal Group Manager, ChipX	DesignCon 2009
C++ IP Design and Reuse Andres Takach, Chief Scientist, Mentor Graphics David Burnette, Senior Software Engineer, Mentor Graphics Michael Fingeroff, Technical Marketing Engineer, Mentor Graphics	DesignCon 2009
Skeleton, An Approach to Maximize Reuse Across Multiple Product Families Michael Rohleder, Technical Staff Engineer, Freescale Semiconductor Stefan Doll, Senior Design Engineer, Freescale Semiconductor Joachim Fader, Verification Lead, Freescale Semiconductor Frank Lenke, Design Manager, Freescale Semiconductor Thomas Lüdeke, Principal Staff Engineer, Freescale Semiconductor Harald Lüpken, Design Lead, Freescale Semiconductor	DesignCon 2009
A Case Study: Critical Area and Critical Feature Analysis of Production 90nm Designs at LSI Corporation David Abercrombie, Program Manager, Mentor Graphics Mark Ward, Product Engineering Director, LSI Corporation Milind Sonawane, Staff Product Engineer, LSI Corporation Cosmin Cazan, Intern, Mentor Graphics	DesignCon 2009
Equation-Based DRC: A Novel Approach to Resolving Complex Nanometer Design Issues David Abercrombie, Program Manager, Mentor Graphics John Ferguson, Senior Technical Marketing Engineer, Mentor Graphics	DesignCon 2009
A Self-Adaptable Slew Rate Control, Variable Power Supply Output Buffer for Embedded Microcontroller Applications with EMI Improvement Using Geometric-Load-Slew Factor Approach Alfredo Olmos, Senior IC Design Engineer, Freescale Semiconductor Andre Luis Vilas Boas, Analog Design Engineer, Freescale Semiconductor Eduardo Ribeiro da Silva, Analog Design Engineer, Freescale Semiconductor Ricardo Maltione, Senior IC Design Engineer, Freescale Semiconductor	DesignCon 2009
Analog Chip-Level Behavioral Modeling Using SVM Kernel-Based Data Mining Techniques Hui Li, Senior Software Engineer, National Semiconductor Rajesh Berigei, Senior Manager, National Semiconductor Sury Maturi, Director, National Semiconductor Li-C Wang, Associate Professor, University of California, Santa Barbara	DesignCon 2009
Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency Kazi Asaduzzaman, Design Engineer, Altera Corporation Sergey Shumarayev, Director of Engineering, Altera Corporation Tim Hoang, Senior Manager, Altera Corporation Leon Zheng, Design Engineer, Altera Corporation	DesignCon 2009
System IO Planning and Design Feasibility – Challenges and Solutions Kevin Rinebold, Product Marketing Manager, Sigrity	DesignCon 2009
Design Optimization of High Speed Digital System Bhyrav Mutnury, Design Engineer, IBM Moises Cases, Distinguished Engineer, IBM Nam Pham, Principal Designer and Architect, IBM Navraj Singh, Graduate Student, Stanford University	DesignCon 2009
Time and Frequency Analysis of Signal and Power Noise of a Microcontroller (ìC) plus its Packaging (LQFP+PCB) Ekkehard Miersch, Senior Consultant, EFM Consulting Mehmet Goekcen, Design Engineer, Infineon Technologies Thomas Steinecke, Principal EMC Design MicroController, Infineon Technologies	DesignCon 2009
The Effects of Chip and Board Behavior on Package-Centric, System-Aware Power Delivery Design Virendra Adsure, Senior Engineer, Intel Long Wang, Engineering Manager, Intel Jiang Li, Senior Application Engineer, Sigrity	DesignCon 2009
How to quickly create complicated message sequence charts automatically without spending money on software Debra Klopfenstein, Architect, SGI	DesignCon 2008
Design and Verification of Ratioed Synchronous Clocks (RSC) for High-Performance Low-Power Processors Ping Yeung, Product Manager, Mentor Graphics Chris Kwok, Engineering Project Lead, Mentor Graphics Matt Berman, Staff Software Engineer, Mentor Graphics Scott Wakefield, Design Engineer, Sun Microsystems Harry Stuimer, Senior Staff Engineer, Sun Microsystems Catherine Ahslchlager, Manager, Sun Microsystems Eugena Talvola, Verification Engineer, Sun Microsystems	DesignCon 2008
ESL Driven Instrumentation Interfaces Mark Burton, Founder, GreenSocs Neal Stollon, Principal Engineer, HDL Dynamics	DesignCon 2008
A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization Kazi Asaduzzaman, Design Engineer, Altera Corporation Sergey Shumarayev, Director of Engineering, Altera Corporation Tim Hoang, Senior Manager, Altera Corporation Kang-Wei Lai, Senior Member of Technical Staff, Altera Corporation Wanli Chang, Senior Member of Technical Staff, Altera Corporation Leon Zheng, Design Engineer, Altera Corporation Mian Smith, Senior Member of Technical Staff, Altera Corporation	DesignCon 2008
On-Chip Instrumentation for In-System IP Validation of a 6 Gbps Serial ATA Platform Device Martin Schrader, Staff Engineer Digital Design, Infineon Technologies Miron Abramovici, CTO, DAFCA, Inc. Daniel Hoggar, Director of Applications Engineering, DAFCA, Inc.	DesignCon 2008
HW / SW Partitioning Trade-offs in 3G & WiMAX Wireless Base-Stations Jakob Saxtorph, System Architect, Integrated Device Technology	DesignCon 2008
Transaction Level Assertions in an Interface Definition Language Dave Whipp, Verification Architect, NVIDIA	DesignCon 2008
Design and Application of Embedded Waveform Viewing Technology for Integrated Circuits Gary McCormack, Director, Office of Strategy and Technology, Vitesse Semiconductor Ian Kyles, Director of Engineering, Vitesse Semiconductor Eric Sweetman, Senior Applications Engineer, Vitesse Semiconductor	DesignCon 2008
Methods for Configurable Hardware Design Craig Rawlings, Director of Marketing, Kilopass Technology	DesignCon 2008
Multimedia Application Specific Engine Design Using High Level Synthesis Nitin Chawla, Member of Technical Staff, STMicroelectronics Roberto Guizzetti, DSP Architect, STMicroelectronics Yan Méroth, DSP Architect, STMicroelectronics Arnaud Deleule, DSP Architect, STMicroelectronics Vishal Gupta, Engineer, STMicroelectronics Pascal Urard, High-Level Synthesis Manager, STMicroelectronics Vinod Kathail, CTO, Synfora	DesignCon 2008
Evaluating Embedded Non-Volatile Memory for 65nm and Beyond Wlodek Kurjanowicz, CTO, Sidense	DesignCon 2008
Using Programmable Logic for Receiver Offset and Yield Enhancement Tina Tran, Senior Design Manager, Altera Corporation Simar Maangat, Design Engineer, Altera Corporation Toan Nguyen, Design Engineer, Altera Corporation Sergey Shumarayev, Director of Engineering, Altera Corporation Wilson Wong, Principal Design Engineer, Altera Corporation Tim Hoang, Senior Manager, Altera Corporation	DesignCon 2008
Packaging DfM into Design Services Flavio Cali, Staff Engineer, Silicon & Software Systems	DesignCon 2008
Simulation and Characterization of GHz On-Chip Power Delivery Network (PDN) Woong Hwan Ryu, Staff Analog Engineer, Intel Vishram Pandit, Senior Analog Design Engineer, Intel Kirupa Pushparaj, Senior Analog Engineer, Intel Sankalp Ramanujam, Analog Engineer, Intel Farag Fattouh, Senior Staff Engineer, Intel	DesignCon 2008
Process and Temperature Variations on Electrical Parameters of Wire-Bond BGA Packages: an Impact Analysis Using Simulation-Based DOE Methodology Hong Shi, Technical Lead, Altera Corporation Hui Liu, Member of Technical Staff, Altera Corporation	DesignCon 2008
FPGA I/O Timing Variations Due to Simultaneous Switching Outputs Iliya Zamek, Member Technical Staff, Altera Corporation Zhe Li, Senior Product Engineer, Altera Corporation Peter Boyle, Manager, Altera Corporation Bozidar Krsnik, Engineer, Altera Corporation	DesignCon 2008
Techniques for Co-Design of the Power Supply Chain from IC to Printed Circuit Board David Quint, Master Engineer, Hewlett-Packard Charles Keen, Analog Engineer, Hewlett-Packard	DesignCon 2008
Interface Based Design Concepts for IC <=> PKG <=> PCB Co-design Bill McCaffrey, Senior Architect, Cadence Design Systems Vikas Kohli, Senior Architect, Cadence Design Systems	DesignCon 2008
Modeling FPGA Current Waveform and Spectrum and PDN Noise Estimation Iliya Zamek, Member Technical Staff, Altera Corporation James Drewniak, Professor, University of Missouri-Rolla Zhe Li, Senior Product Engineer, Altera Corporation Peter Boyle, Manager, Altera Corporation Shishuang Sun, Senior Engineer, Altera Corporation Xiaohe Chen, PhD candidate, University of Missouri-Rolla Tun Li, MS student, University of Missouri-Rolla Sandeep Chandra, MS student, University of Missouri-Rolla Daryl Beetner, Associate Professor, University of Missouri-Rolla	DesignCon 2008
IP Solves the Increasing Challenge of Implementing an Interface to Off-Chip DDR SDRAM Graham Allan, Director of Marketing, MOSAID Jody Defazio, Director of Engineering, MOSAID	DesignCon 2007
Architectural Requirements of an Oversubscribed Ethernet MAC Uday Mudoi, Product Marketing Manager, Vitesse Semiconductor Brian Branscomb, System Architect, Vitesse Semiconductor	DesignCon 2007
Request-Response Trace for Bus Performance Analysis Neal Stollon, Director of Technical Marketing, First Silicon Solutions Bruce Ableidinger, Director of Business Development, First Silicon Solutions	DesignCon 2007
Creating a Generic Behavioral Model – DDR based memory system using SystemC/TLM Leena Singh, Verification Architect, Rambus Inc. Praveen Prakash, Senior Member of Technical Staff, Rambus Inc.	DesignCon 2007
FPGA Design for Signal and Power Integrity Hong Shi, Technical Lead, Altera Corporation Larry Smith, Principal Engineer, Altera Corporation	DesignCon 2007
Methodology to Analyze and Insert a Power Mesh Early in Design Cycle Ken Umino, Staff Consultant, Synopsys Evan Chen, Design Consultant, Synopsys Joseph Schrand, IC Design Engineer, Thomson	DesignCon 2007
Calibration Techniques for High-Bandwidth Source-Synchronous Interfaces Manoj Roge, System Architect, Altera Corporation Andy Bellis, Team Leader, Altera Corporation Phil Clarke, Senior Design Engineer, Altera Corporation Joseph Huang, Manager, Altera Corporation Michael Chu, Supervising Member of Technical Staff, Altera Corporation Yan Chong, Engineer, Altera Corporation	DesignCon 2007
RFID Radio Circuit Design in CMOS Lawrence Williams, Director of Business Development, Ansoft Corporation Daniel Wu, RF and Mixed-Mode Specialist, Ansoft Corporation Minhong Mi, Applicaiton Engineer, Ansoft Corporation	DesignCon 2007
Practical Clock Skew Scheduling on a High Performance Processor Alex Rubin, Advisory Engineer, IBM Uwe Fassnacht, Senior Technical Staff Member, IBM Frank Borkam, Senior Applications Engineer, IBM Paul Campbell, Member of Technical Staff, IBM	DesignCon 2007
Moving Manufacturing More Effectively Into Design Marc Levitt, Vice President DFM, Cadence Design Systems	DesignCon 2007
Optimizing Memory Interfaces for Specific Applications Olivier Despaux, Senior Strategic Applications Engineer, Xilinx	DesignCon 2007
Selection Criteria for Using DDR, GDDR or MobileDDR Memories in System Designs Raj Mahajan, Chief Architect, MemCore	DesignCon 2007
Low Latency PCI-Express Impacts System Architecture Trade-offs Hemant Gavali, Senior Design Engineer, Ingot Systems Pushkar Upadhye, Senior Design Engineer, Ingot Systems	DesignCon 2007
High Performance Image Interfaces In Low Cost Programmable Logic Gordon Hands, Director of Strategic Marketing, Lattice Semiconductor	DesignCon 2007
Unifying Residential Systems – Wired verses Wireless Infrastructures Richard Zarr, Worldwide Partnership Marketing Manager, National Semiconductor	DesignCon 2007
Comparison of a 1x Clock DDR Design Versus a 2x Clock DDR Design Ken Umino, Staff Consultant, Synopsys Peter Thoeming, Senior Member of the Technical Staff, Thomson	DesignCon 2007
Acceptance Criteria for a High Definition Video Encoder Raghavan Menon, CTO, Ingot Systems Krishna Ramaswamy, Senior Design Engineer, Ingot Systems	DesignCon 2007
Memory Design Considerations when Migrating to DDR3 Interfaces from DDR2 Raj Mahajan, Chief Architect, MemCore	DesignCon 2007
Packaging a Supercomputer in a PCI Express Form Factor Greg Edlund, Senior Engineer, IBM Mark Bailey, Advisory Engineer, IBM Bob Morse, Principal Hardware Design Engineer, Mercury Computer Systems Ankur Patel, Signal Integrity Engineer, IBM	DesignCon 2007
Selecting the Best Package Type for Your Design – Today and Tomorrow Gregory Phipps, Design Manager, Advanced Interconnect Technologies	DesignCon 2007
Signal Integrity Analysis for Inductively Coupled Connectors and Sockets Karthik Chandrasekar, Graduate Student, North Carolina State University John Wilson, Research Assistant Professor, North Carolina State University Evan Erickson, Graduate Student, North Carolina State University Zhiping Feng, Research Associate, North Carolina State University Jian Xu, Graduate Student, North Carolina State University Stephen Mick, Research Associate, North Carolina State University Paul Franzon, Professor, North Carolina State University	DesignCon 2007
Applications of Optimization Routines in Signal Integrity Analysis Erik Daniel, Staff Scientist, Mayo Clinic Barry Gilbert, Staff Scientist, Mayo Clinic Pat Zabinski, Principal Engineer, Mayo Clinic Ben Buhrow, Project Engineer, Mayo Clinic	DesignCon 2007
Methodology to Generate Frequency Domain Specification from Eye Masks using Statistical Analysis Seungyong Baek, Staff Engineer, Silicon Image Namhoon Kim, Signal Integrity Engineer, Silicon Image Ju Hwan Yi, Staff Engineer, Silicon Image Eric Lee, Manager, Silicon Image Baegin Sung, Senior Manager, Silicon Image Joungho Kim, Professor, KAIST	DesignCon 2007
Impulse Response Characterization of Operating Margin in High-Speed Communication Channels David Brunker, Technical Fellow, Molex Gourgen Oganessyan, Senior Electrical Engineer, Molex Pravin Patel, Senior Engineer, IBM	DesignCon 2007
Differential PCB Structures using Measured TRL Calibration and Simulated Structure De-Embedding Mike Resso, Business Development Manager, Agilent Technologies Ming Tsai, Staff Hardware Development Engineer, Xilinx Heidi Barnes, Senior Test Consultant, Verigy Antonio Ciccomancini Scogna, Applicaiton Engineer, CST of America	DesignCon 2007
Comparison of S-Parameter Concatenation to Full-Wave Simulation for High-Speed Interconnect Analysis Stephen Smith, Staff Signal Integrity Engineer, FCI Vittal Balasubramanian, Senior Signal Integrity Engineer, FCI Sedig Agili, Associate Professor, Pennsylvania State University	DesignCon 2007
Application of Embedded Capacitor Technology for High Performance Semiconductor Packaging Dan Amey, Research Fellow, DuPont Electronic Technologies Karl Dietz, Technology Manager, DuPont Electronic Technologies	DesignCon 2007
Reuse or Recycling? A Practical Approach for Designers Tom Dewey, Technical Marketing Engineer, Mentor Graphics Michael Lee, Marketing Group Manager, Mentor Graphics	DesignCon 2006
A Taxonomy for the Electronic System Level (ESL) Brian Bailey, Consultant, Brian Bailey Consulting	DesignCon 2006
Complex clock issues and how Platform ASICs address them Greg Martin, Senior Product Application Engineer, LSI Logic Jonathan Byrn, Methodology Development Engineer, LSI Logic Grant Lindberg, Marketing Applications Director, LSI Logic	DesignCon 2006
Tricks and Techniques for Implementing High-Performance PCI-Express Interfaces in FPGAs and ASICs Warren Miller, VP Marketing, Ingot Systems Pushkar Upadhye, Engineering manager, Ingot Systems	DesignCon 2006
Leveraging System-C Transaction-Level Models for Architectural Exploration, Algorithm Development, and Large Configuration Evaluation Terry Doherty, Principal Engineer, Emulex Corporation	DesignCon 2006
A Comparative Study on the Effectiveness of Automated Assertions Versus Traditional Methods in a Project Design Flow Andreas Meyer, Chief Technology Officer, Assertive Design	DesignCon 2006
Why did my chip do that? A survey of on-chip debug and diagnosis techniques Brian Bailey, Consultant, Brian Bailey Consulting Carina Chiang, Program Manager, Agilent Technologies	DesignCon 2006
Design and Analysis for Variability in Nanometer Technologies Ajay Bhatia, Technical Lead and Senior Design Manager, Sun Microsystems Sagar Reddy, Member of Technical Staff, Sun Microsystems Shashank Shastry, Member of Technical Staff, Sun Microsystems	DesignCon 2006
New Era for RF CMOS Design Lawrence Williams, Director of Business Development, Ansoft Corporation Daniel Wu, RF and Mixed-Mode Specialist, Ansoft Corporation Albert Yen, Mixed-Mode and Radio Frequency Technology Manager, UMC	DesignCon 2006
Manufacturability Studies of X Architecture Diagonal Lines Narain Arora, Vice President of Technology, Cadence Design Systems Kalyan Thumaty, Vice President and General Manager, Cadence Design Systems	DesignCon 2006
Overcoming Signal Integrity Issues with Wideband Crosstalk Cancellation Technology Michael Vrazel, Technical Director, Quellan Andrew Kim, Senior System Architect, Quellan	DesignCon 2006
A Framework for Optimal Utilization of Hardware Resources in Complex FPGA Devices Henry Yu, Principal Engineer and Senior R&D Manager, Mentor Graphics Mandar Chitnis, Development Engineer, Mentor Graphics Rakesh Jain, Technical Marketing Engineer, Mentor Graphics Darren Zacher, Technical Marketing Engineer, Mentor Graphics	DesignCon 2006
The Impact of DFM in the Design Phase below 90 Nanometers Marc Levitt, Vice President of Design for Manufacturing, Cadence Design Systems	DesignCon 2006
A Fast Methodology for Static Power IP Characterization Peter Chen, Senior Project Manager, Faraday Technology Corporation Sammy Lee, Engineer, Faraday Technology Corporation Jim Wang, Engineer, Faraday Technology Corporation Peter Pong, Engineer, Faraday Technology Corporation Harrison Liu, Engineer, Faraday Technology Corporation Alvin Chen, Engineer, Faraday Technology Corporation	DesignCon 2006
Design of a 400MHZ DDR2 Memory Controller for a High-Performance CPU Application Warren Miller, VP Marketing, Ingot Systems Raghavan Menon, CTO, Ingot Systems	DesignCon 2006
Ultra Low-Power System Design in Deeply Embedded Applications Mark Buccini, Director of Marketing, Texas Instruments	DesignCon 2006
Hardware Firmware Partitioning of the WiMedia Ultra-Wideband MAC based on Performance Analysis Debashis Goswami, Technical Manager, MindTree Consulting Pvt Vivek Padi, Design Engineer, MindTree Consulting Pvt Santosh Hegde, Design Engineer, MindTree Consulting Pvt	DesignCon 2006
Back-End Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design Ken Umino, Staff Consultant, Synopsys Ross Segelken, Research and Development Engineer, Synopsys John Stonick, Synopsys Scientist, Synopsys Bill Beale, Application Engineer, Synopsys	DesignCon 2006
AëS - Application Lambda Switching Victor Rychlicki, Principle Designer, Rychtronix Mind Werkz	DesignCon 2006
Designing A Real-Time HDTV 1080p Baseline H.264/AVC Encoder Core Vincenzo Liguori, Founder, Ocean Logic Pty Kevin Wong, Engineer, Ocean Logic Pty	DesignCon 2006
Frequency-Dependent Physical-Statistical Material Property Extraction for Tabular W-element Model Based on VNA Measurements Dong-Ho Han, Senior Package Engineer, Intel Myoung Joon Choi, Senior Analog Engineer, Intel Jungwok Suk, a Senior Analog Engineer, Intel Woong Hwan Ryu, Staff Analog Engineer, Intel	DesignCon 2006
The myth about ground and how to correctly use it in high-speed Signal Integrity and Power Integrity modeling and simulation Zhiping Yang, Principal Signal Integrity Engineer, Apple Computer	DesignCon 2006
Analysis of FPGA Simultaneous Switching Noise in Three Domains: Time, Frequency, and Spectrum Hong Shi, Member of Technical Staff, Altera Corporation Geping Liu, Engineer, Altera Corporation Alan Jian Liu, Packaging Design Engineer, Altera Corporation	DesignCon 2006
Fast Time-Domain Simulation of 200+ Port S-parameter Package Models Vadim Heyfitch, MTS Engineer, Altera Corporation Vladimir Dmitriev-Zdorov, Engineer, Mentor Graphics Gary Pratt, Manager, Mentor Graphics Sherri Azgomi, Senior Applications Engineer, Altera Corporation	DesignCon 2006
Design, Analysis and Experimental Verification of an Equalized 10Gbps Link Young Kwark, Research Staff Member, IBM Lei Shan, Research Staff Member, IBM Christian Baks, Engineer, IBM Jean Trewhella, Manager, IBM Petar Pepeljugoski, Research Staff Member, IBM Mounir Meghelli, Research Staff Member, IBM Troy Beukema, Research Staff Member, IBM Mark Ritter, Research Staff Member, IBM	DesignCon 2006
Impedance Matching Techniques for VLSI Packaging Sunil Khatri, Assistant Professor, Texas A&M University Brock LaMeres, Hardware Design Engineer, Agilent Technologies Rajesh Garg, MTS II, Texas A&M University Kanupriva Gulati, Doctoral Student, Texas A&M University	DesignCon 2006
S-Parameter characterization of sockets Jan De Geest, Research and Development Engineer, FCI Stefaan Sercu, Manager, FCI Dana Bergey, Manager, FCI Willem Dalinghaus, Trainee, FCI	DesignCon 2006
Full Wave Simulation and Validation of a Simple Via Structure Christian Schuster, Research Staff Member, IBM Bruce Archambeault, Distinguished Engineer, IBM Samuel Connor, Senior Engineer, IBM Daniel de Araujo, Senior Engineer, IBM Mohammed Reza Hashemi, Electrical Engineering, IBM Raj Mittra, Professor of Electrical Engineering, IBM Albert Ruehli, Research Staff Member, IBM	DesignCon 2006
Slow-Wave Causal Model for Multi Layer Ceramic Capacitors Jason Miller, Staff Engineer, Sun Microsystems Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems Gustavo Blando, Signal Intergrity Engineer, Sun Microsystems	DesignCon 2006
Effects of Infiniband Fixture Crosstalk on Synthesized Eye Diagram Eugene Mayevskiy, Applications Engineer, Tektronix	DesignCon 2006
Static Timing Analysis in Ultra-Deep Micron Technologies Anthony Sanders, Principal Engineer, Infineon Technologies Birgit Sanders, Staff Engineer, Infineon Technologies	Euro DesignCon 2005
Physical Optimization Algorithms for Timing Closure Peter Suaris, Chief Scientist, Mentor Graphics Nan-Chi Chou, Engineering Development Director, Mentor Graphics	Euro DesignCon 2005
A Flexible and Adaptive Pipelining Concept for Low-Latency Interconnects Markus Bühler, Methodology Engineer, IBM	Euro DesignCon 2005
Addressing Design for Manufacturability (DFM) Issues in Nanometer Designs and Beyond Ganesan Nagasubramanian, Project Manager, Infineon Technologies Murali Sundaram, Design Engineer, Infineon Technologies Manoj Sundareswaran, Senior Design Engineer, Infineon Technologies Arun Venkatesan, Design Engineer, Infineon Technologies Balamurugan Selvaraj, Senior Design Engineer, Infineon Technologies Jagadeesh Kotturashettar, Senior Design Engineer, Infineon Technologies	Euro DesignCon 2005
Modeling Complex Silicon Effects in Nanometer Designs Carey Robertson, Product Development Manager, Mentor Graphics	Euro DesignCon 2005
EDA Platform: Buzzword or True Technological Benefit? John Ferguson, Senior Technical Marketing Engineer, Mentor Graphics	Euro DesignCon 2005
Challenges in PowerPC440-FS Soft Core Development: Timing perspective Kaijian Shi, Principal Consultant, Synopsys Terry Biggs, Project Manager, Hewlett-Packard Ken Umino, Staff Consultant, Synopsys	Euro DesignCon 2005
Galvanic Isolation Using Capacitive Coupling -- CMOS-Technology Allows 100Mbps and High Integration Frank Dehmelt, Application Engineer, Texas Instruments	Euro DesignCon 2005
A High Integration System IC with High Power Capability and Serial Interface in an Automotive Environment Martin Kaltenegger, Engineer, Infineon Technologies	Euro DesignCon 2005
Design and Thermal Management of Power Distribution Units for Automotive Applications Stefan Masek, Supervisor, FEM Group, Tyco Electronics Andre Dressel, Development Engineer, Tyco Electronics	Euro DesignCon 2005
Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures Thomas Schweizer, Research Assistant, Tübingen University Julio Oliveira Filho, Research Assistant, Tübingen University Tobias Oppold, Research Assistant, Tübingen University Tommy Kuhn, Research Assistant, Tübingen University Wolfgang Rosenstiel, Professor, Tübingen University	Euro DesignCon 2005
Build and Verify Sophisticated System-On-Chip Designs in Minutes by Leveraging the Power of SPIRIT Format Alexander Hahn, Engineer, Mentor Graphics	Euro DesignCon 2005
Full Chip Simulation Enables Pre-Silicon Software Development Michael Rohleder, Technical Staff Engineer, Freescale Semiconductor Manfred Thanner, Senior Systems Staff Engineer, Freescale Semiconductor Stephen Müller, Senior Staff Field Application Engineer, Freescale Semiconductor Andreas Kirschbaum, Manager, Continental Teves	Euro DesignCon 2005
DSP Synthesis: A Breakthrough for System-Level FPGA Designers Dirk Seynhaeve, Director of Corporate Applications Engineering, Synplicity Pierluigi lo Muzio, Engineer, Synplicity	Euro DesignCon 2005
A Novel Technique for VCO Design Having Multiple Tuning Ranges with Inbuilt Digital Controller Madan Vemula, Analog Design Engineer, Talent Telecom Solutions	Euro DesignCon 2005
Improving the IP Evaluation Process Saverio Fazzari, Technical Marketing Director, Cadence Design Systems	Euro DesignCon 2005
Bypass Filter Design Considerations for Modern Digital Systems: A Comparative Evaluation of the Big “V”, Multi-pole, and Many Pole Bypass Strategies Steve Weir, Consultant, Teraspeed Consulting Group	DesignCon East 2005
Joint Effect of Simultaneous Switching Noise and IO Return Current for CMOS FPGA Package Hong Shi, Member of Technical Staff, Altera Corporation	DesignCon East 2005
A VITA Based Framework for Ruggedized COTS Electronics with Emphasis on Liquid Cooling - VITA 48 Randy Banton, Vice President, Defense Electronics Engineering, Mercury Computer Systems Donald Blanchet, Consulting Mechanical Engineer, Mercury Computer Systems	DesignCon East 2005
A Black-Box Frequency Dependent Model of Capacitors for Frequency Domain Simulations Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems	DesignCon East 2005
Functional Verification of ATM Related Protocols for Communication Processor Boaz Shahar, Project Leader, Freescale Semiconductor	DesignCon East 2005
Using Yield-Focused Design Methodologies to Speed Time-to-Market Marc Levitt, Vice President DFM, Cadence Design Systems	DesignCon East 2005
Essential Measurement Considerations When Using Extracted-Clock Timing References Jim Stimple, Department Scientist, Agilent Technologies Greg Le Cheminant, Applications and Market Development Engineer, Agilent Technologies	DesignCon East 2005
Methodology for Jitter Measurement Correlation and Consistency Ransom Stephens, Physicist, Agilent Technologies Daniel Chow, Senior Member of Technical Staff, Altera Corporation	DesignCon East 2005
Standards-compliant IP Design Advantages, Problems, and Future Directions Amir Hekmatpour, Senior Engineer, IBM Kenneth Goodnow, Senior Engineer, IBM	DesignCon East 2005
Extraction and Implementation of Effective Mismatch Models David Potts, Principal Design Engineer, Fairchild Semiconductor Timwah Luk, Director of Modeling, Fairchild Semiconductor	DesignCon East 2005
VHDL-200X: The Future of VHDL Jim Lewis, Principal Trainer, SynthWorks VHDL Training	DesignCon East 2005
Solving Signal Integrity Challenges with Advanced Package Designs Suresh Subramaniam, Sr. Design Engineer, Xilinx Mark Alexander, Senior Product Application Engineer, Xilinx	DesignCon East 2005
Design for Portability Greg Martin, Senior Product Application Engineer, LSI Logic	DesignCon East 2005
Customized Synthesis for 90 nm Structured ASICs -- Delivering Higher Performance, Faster Time to Market and Reduced Work on the Back End Mark Fox, Engineer, NEC Electronics America John Gallagher, Senior Marketing Director, Synplicity	DesignCon East 2005
Implementing High-Speed SPI-4.2 Interfaces Using FPGAs Ali Burney, Senior Product Planning Engineer, Altera Corporation Sanjay Charagulla, System Architect, Altera Corporation	DesignCon 2005
DSP Teams with Embedded CPU for Embedded Workloads Chris Fogelklou, Applications Engineer, National Semiconductor	DesignCon 2005
Soft Error Radiation Test, Simulation and Protection in Nanometer Technologies Damien Chardonnereau, Product Manager, iRoC Technologies	DesignCon 2005
Raising the Level of Abstraction for Design and Verification Victor Berman, Group Director of Language Standards, Cadence Design Systems	DesignCon 2005
Setting the Standard for Debug & Trace in Multi-core SoCs William Orme, Product Manager, ARM	DesignCon 2005
Ultra-Wideband Radio Design for Multi-band OFDM 480 Mb/s Wireless USB Lawrence Williams, Director of Business Development, Ansoft Corporation Daniel Wu, RF and Mixed-Mode Specialist, Ansoft Corporation Eldon Staggs, Senior Applications Engineer, Ansoft Corporation Albert Yen, Mixed-Mode and Radio Frequency Technology Manager, UMC	DesignCon 2005
SystemVerilog Implicit Port Connections Clifford Cummings, President, Sunburst Design	DesignCon 2005
Hardware Implementation of a Tree Based IP Lookup Algorithm for OC-768 and Beyond Florin Baboescu, Researcher, STMicroelectronics Suresh Rajgopal, Principal Engineer, STMicroelectronics Lun-Bin Huang, Sr. Principal Engineer, STMicroelectronics Nick Richardson, Fellow, STMicroelectronics	DesignCon 2005
An Advanced Methodology for On-Chip Passive Component Design and Optimization Albert Yen, Mixed-Mode and Radio Frequency Technology Manager, UMC Steve Rousselle, Application Engineering Manager, Ansoft Corporation Bryan Boots, Application Engineer, Ansoft Corporation	DesignCon 2005
“Fearless Partitioning”: An Efficient Approach to the Challenges of a True Multi-Chip Integration Herve Menager, SoC Architect, Philips Semiconductors Ramaprasad Kadiyala, Senior Designer, Philips Semiconductors	DesignCon 2005
A Method for Analyzing Full Chip PI and EMI Using Parallel Processed PEEC Model Norio Matsui, President, Applied Simulation Technology Dileep Divekar, Vice President, Applied Simulation Technology Neven Orhanovic, Engineer, Applied Simulation Technology Fujihiko Sugihashi, Design Engineer, Texas Instruments Takeshi Nosaka, Design Engineer, Texas Instruments Koji Yamazaki, Design Engineer, Texas Instruments	DesignCon 2005
Challenges to Silicon Modeling in the Nanometer Era Carey Robertson, Product Development Manager, Mentor Graphics	DesignCon 2005
Joint Study of Simultaneous Switching Noise and IO Return Current for CMOS FPGA Package Hong Shi, Member of Technical Staff, Altera Corporation	DesignCon 2005
Z-Axis Power Delivery: Concept and Implementation Augusto Panella, Engineering Manager, Molex	DesignCon 2005
ARM1136 Low Power Test Chip -- Case Study for 90nm Low Power Implementation Peter Bennett, Chief Consulting Engineer, Cadence Design Systems George Kuo, Technical Director, Cadence Design Systems	DesignCon 2005
Integrated Design for IA-64 Microprocessor Power Delivery System Yong Wang, Electrical Engineer, Hewlett-Packard David Quint, Master Engineer, Hewlett-Packard Tim Michalka, Manager, Hewlett-Packard Karl Bois, Signal Integrity Engineer, Hewlett-Packard	DesignCon 2005
Low Power Design Methodologies and Optimizations for Sub-90nm ASIC Kaijian Shi, Principal Consultant, Synopsys Jason Binney, Application Engineer, Synopsys	DesignCon 2005
Power and Timing Closures for IC and Package Co-Design Ching-Chao Huang, Senior Vice President of Business Development, Optimal Corp.	DesignCon 2005
Design of a Low-Power Differential Repeater Using Low Voltage and Charge Recycling Brock LaMeres, Ph.D. candidate, University of Colorado Sunil Khatri, Assistant Professor, Texas A&M University	DesignCon 2005
Co-Design in the PA-8800 Microprocessor Tim Michalka, Manager, Hewlett-Packard Karl Bois, Signal Integrity Engineer, Hewlett-Packard Mark Frank, Signal Integrity Engineer, Hewlett-Packard Shaw Moldauer, Hardware Design Engineer, Hewlett-Packard	DesignCon 2005
Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package Robert Markunas, Vice President of Market Development, Ziptronix

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