Today's SoC designers face an increasingly daunting task when they are required to develop an SoC that requires a DDR SDRAM interface. Problems include the requirement for both ASIC and mixed-signal design flows, complex verification, intimacy with the DRAM components (and the road maps), and short chip life cycles and time to market. Fortunately, there is a semiconductor IP solution that addresses these problems and reduces development costs as well. Licensing an advanced process-independent DDR SDRAM memory controller in combination with the process-specific physical interface provides a silicon proven solution that also significantly reduces overall design risk.

The performance of power distribution networks is critical to high-speed digital circuits in terms of both signal integrity and radiated emission. This paper studies charge delivery of a power distribution network, as well as power bus noise resulting from device switching, in the time domain as well as the frequency domain. Some of the PDN performance analysis is easier to understand when analyzed in the time domain. The effects of capacitor location, capacitor value, power/ground plane pair location within the stackup, board size, and dielectric material, are discussed.