Most new digital systems require amounts of memory larger that can be embedded in ASSP or FPGA devices. This paper discusses two aspects of the design—memory interface architectural choices and implications—and several implementation aspects of the memory interface, aimed at increasing robustness and reducing power for the interface. Experimental results are used to illustrate the concepts addressed in the paper.

This paper presents a method for testing jitter tolerance of SerDes receivers using the timing misalignment between the jittered source clock and the recovered clock. The method injects random jitter into the serial bit stream and measures the jitter transfer function of the CDR in the SerDes receiver to estimate the jitter tolerance. The paper derives an equation for estimating BER accurately using jitter transfer function of SerDes CDRs. The method is much faster than the conventional BERTS method. The accuracy and test speed of the method are verified by 2.5 Gbps SerDes experiments.