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From a full library of technical papers, to video keynote presentations from leading industry experts, the InfoVault offers key insight on the business and technical issues facing electronic design and semiconductor industries.

HIGHLIGHTED PAPERS

2009 Paper Award Winner
Michael Steinberger, Distinguished Member of Technical Staff, SiSoft
Chong Ding, Signal Integrity Engineer, Cisco Systems
Divya Gopinath, Intern, Cisco Systems
Stephen Scearce, Manager, Cisco Systems
Doug White, Technical Leader, Cisco Systems
Vias play a critical role in the high frequency electrical behavior of packages and printed circuit boards. Although measured data and electromagnetic solvers can be used to study via electrical properties, a clearer description of the underlying physics would make engineering judgment concerning vias more effective. This paper introduces a simple experiment and corresponding textbook solution for radial TEM waves which demonstrates the physics of vias. Extensions of this experiment show how the underlying physical model can be used to explain the behavior of differential vias, ground vias, and via antipads.

2009 Paper Award Winner
Mike Resso, Business Development Manager, Agilent Technologies
Eric Bogatin, President, Bogatin Enterprises
Sanjeev Gupta, Signal Integrity Applications Expert, Agilent Technologies
Lambert Simonovich, Backplane Specialist, Nortel
This paper presents a method for testing jitter tolerance of SerDes receivers using the timing misalignment between the jittered bit clock and the recovered clock. To estimate the jitter tolerance, the method first injects random jitter into the serial bit stream and measures the jitter transfer function of the CDR in the SerDes receiver. The paper derives an equation for estimating BER accurately using the jitter transfer function of SerDes CDRs. The method is much faster than the conventional BERTS method. The accuracy and test speed of the method are verified by 2.5 Gbps-SerDes experiments.
KEYNOTES FROM DESIGNCON 2009
Mark Gogolewski
Chief Technology Officer
Denali Software
Walden Rhines
Chairman and Chief Executive Officer
Mentor Graphics
Paolo Gargini
Director, Technology Strategy
Intel
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PODCASTS
Mick Posner, Product Manager, DesignWare® IP Solutions, Synopsys

Lior Amarilio, Chief Architect, R&D, ChipX

John Pickerd, Principal Engineer, Tektronix

Rajeev Ranjan, Chief Technology Officer, Jasper Design Automation

Chad Morgan, Principal Engineer, Circuits and Design, Tyco Electronics

Syed Bokhari, Lead SI and EMC Specialist, Fidus Systems

Douglas Smith, Engineering Consultant, D. C. Smith Consultants

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