2012 Paper Award Finalists
2012 Paper Award Finalists
Track: High-Speed Serial Design
A Comparison of 25 Gbps NRZ & PAM-4 Modulation Used in Legacy & Premium Backplane Channels
Adam Healey, LSI Corporation
Chad Morgan, TE Connectivity
Track: Memory and Parallel Interface Design
A Zero Sum Signaling Method for High Speed, Dense Parallel Bus Communications
Chad M. Smutzer, Mayo Clinic
Robert W. Techentin, Mayo Clinic
Michael J. Degerstrom, Mayo Clinic
Dr. Barry K. Gilbert, Mayo Clinic
Dr. Erik S. Daniel, Mayo Clinic
Track: High-Speed Timing, Jitter and Noise Analysis
Accurate Analytical Model of Bounded Uncorrelated Jitter and Noise Improves the Accuracy of Crosstalk Impaired Link Evaluation: Theory, Validation, Practical Results
Maria Agoston, Tektronix
Pavel Zivny, Tektronix
Track: Memory and Parallel Interface Design
Algorithmic Memory Brings an Order of Magnitude Performance Increase to Next Generation SoC Memories
Sundar Iyer, Memoir Systems
Da Chuang, Memoir Systems
Track: FPGA Design and Debug
An Improved Co-Simulation Approach to Rapidly Prototype, Verify, and Implement Dynamic FPGA-based Embedded Control Systems
Muris Mujagic, National Instruments
Oleg Stepanov, National Instruments
Brian MacCleery, National Instruments
Track: Power Integrity and Power Distribution Network Design
Analysis and Characterization of Supply Noise and Its Jitter Impact in a 12.8Gbps Single-Ended Signaling Memory Interface
Hai Lan, Rambus Inc.
Minghui Han, Rambus Inc.
Wendem Beyene, Rambus Inc.
Chris Madden, Rambus Inc.
Chuck Yuan, Rambus Inc.
Ralf Schmitt, Rambus Inc.
Track: Analog and Mixed-Signal Design and Verification
Analysis of High-Stability Controlled Oscillators for LowBandwidth PLLs
Sassan Tabatabaei, SiTime Corporation
Track: Power Integrity and Power Distribution Network Design
Are Power Planes Necessary for High Speed Signaling?
Suzanne L. Huh, Intel Corporation
Madhavan Swaminathan, Georgia Institute of Technology
Track: High-Speed Serial Design
Backplane Channel Design Optimization: Recasting a 3Gb/s Link to Operate at 25Gb/s and Above
Xiaoxiong Gu, IBM T.J. Watson Research Center, NY
Young H. Kwark, IBM T.J. Watson Research Center, NY
Dazhao Liu, Missouri Institute of Science and Technology, MO
Yaojiang Zhang, Missouri Institute of Science and Technology, MO
Jun Fan, Missouri Institute of Science and Technology, MO
Renato Rimolo-Donadio, Technische Universität Hamburg-Harburg, Germany
Sebastian Müller, Technische Universität Hamburg-Harburg, Germany
Christian Schuster, Technische Universität Hamburg-Harburg, Germany
Francesco de Paulis, University of L’Aquila, Italy
Track: Memory and Parallel Interface Design
Complete Analysis and Design of Power Integrity for Advanced Memory Technology (DDR4)
Brian Wang, Intel Corporation
Vishram S. Pandit, Intel Corporation
Track: PCB Materials, Processing and Characterization
Comprehensive Analysis of Flexible Circuit Materials Performance in Frequency and Time Domains
Glenn Oliver, DuPont Electronics & Communications
Jim Nadolny, Samtec
Deepukumar Nair, DuPont Electronics & Communications
Track: System Co-Design: Chip/Package/Board
Design and Characterization of the Power Supply System for a High Speed 1600 Mbps DDR3 Interface in Wirebond Package
Ralf Schmitt, Rambus Inc.
Hai Lan, Rambus Inc.
Track: High-Speed Serial Design
Design Optimization for Minimal Crosstalk in Differential Interconnect
Beomtaek Lee, Intel Corp.
Xiaoning Ye, Intel Corp.
Raul Enriquez, Intel Corp.
Kai Xiao, Intel Corp.
Ted Ballou, Intel Corp.
Jimmy A Johansson, Intel Corp.
Track: High-Speed Serial Design
Efficient End-to-end Simulations of 25G Optical Links
Sanjeev Gupta, Avago Technologies
Fangyi Rao, Agilent Technologies
Jing-tao Liu, Agilent Technologies
Amolak Badesha, Avago Technologies
Track: PCB Design Tools and Methodologies
Embedded DC Blocking Capacitors in Connectors - Study of Impacts on PCB Design and High Speed Serial Link Performance
Jeremy Buan, Hirose Electric (U.S.A.), Inc.
Toshi Takada, Hirose Electric (U.S.A.), Inc.
Fernando Cheng, Hirose Electric (U.S.A.), Inc.
Jonathan Weng, Hirose Electric (U.S.A.), Inc.
Clement Luk, Hirose Electric (U.S.A.), Inc.
Tats Arai, Hirose Electric (U.S.A.), Inc.
Ching-Chao Huang, AtaiTec Corp.
Douglas Yanagawa, Cisco Systems, Inc.
Phillip I-Chyau Li, Cisco Systems, Inc.
Yaochao Yang, Cisco Systems, Inc.
Track: High-Speed Signal Processing, Equalization and Coding
Enhanced Equalization and Forward Correction Coding Technologies for 25+Gb/s Serial Link System
Cathy Ye Liu, LSI Corporation
Pervez Aziz, LSI Corporation
Adam Healey, LSI Corporation
Track: Chip-Level Design for Signal/Power Integrity
Full System Channel Co-optimization for 28Gb/s SerDes FPGA Applications with Stacked Silicon Interconnect Technology
Namhoon Kim, Xilinx, Inc.
Zhaoyin Daniel Wu, Xilinx, Inc.
Jack Carrel, Xilinx, Inc.
Joong-ho Kim, Xilinx, Inc.
Paul Wu, Xilinx, Inc.
Track: Test and Measurement Methodology
Improvements in time-domain TRL accuracy for transmission measurements
Victor Khilkevich, Missouri University of Science and Technology
Brice Achkir, Cisco Systems, Inc.
James L. Drewniak, Missouri University of Science and Technology
Track:
Investigation of High Speed Serdes Induced EMI and Its Suppressing with Novel Heatsink Design
Zhenggang Cheng, Cisco Systems Inc.
Mike Sapozhnikov, Cisco Systems Inc.
Diaco Davari, Cisco Systems Inc.
Amit Agrawal, Cisco Systems Inc.
Jeffrey Evans, Cisco Systems Inc.
Track: Test and Measurement Methodology
Methodologies and Measurement Comparisons of High-Speed Links Using On-Chip and On-Bench Instrumentations
Wendem T. Beyene, Rambus Inc.
Chris Madden, Rambus Inc.
Track: Electromagnetic Compatibility and Interference
Miniaturization of Common mode filter based on EBG patch resonance
Francesco de Paulis, University of L’Aquila
Bruce Archambeault, IBM
Muhammet Hilmi Nisanci
Sam Connor, IBM
Antonio Orlandi, University of L’Aquila
Track: Test and Measurement Methodology
Mixed-Mode De-embedding Methodology Using Multiline Calibration Structures
Chung-Chi Huang, Inphi Corporation
Track: High-Speed Signal Processing, Equalization and Coding
Mostly Digital SerDes: A Comprehensive Low Power Receiver Architecture
Erik Chmelar, LSI Corporation
Choshu Ito, Kool Chip USA, Inc.
Track: Power Integrity and Power Distribution Network Design
PDN Resonance Calculator for Chip, Package and Board
Larry D Smith, Qualcomm Corporation
Mayra Sarmiento, Altera
Yuri Tretiakov, Altera
Shishuang Sun, Altera
Zhe Li, Altera
Sunitha Chandra, Altera
Track: High-Speed Timing, Jitter and Noise Analysis
Power Supply Noise Induced Jitter in a 6.4Gbps/Link Memory Interface System
Hai Lan, Rambus Inc.
Ravi Kollipara, Rambus Inc.
Sam Chang, Rambus Inc.
Ling Yang, Rambus Inc.
Lei Luo, Rambus Inc.
Kashinath Prabhu, Rambus Inc.
John Eble, Rambus Inc.
Ralf Schmitt, Rambus Inc.
Track: RF/Microwave Techniques for Signal Integrity
Practical Methodology for Analyzing the Effect of Conductor Roughness on Signal Losses and Dispersion in Interconnects
Yuriy Shlepnev, Simberian Inc.
Chudy Nwachukwu, Isola Group
Track: RF/Microwave Techniques for Signal Integrity
The Relationship Between Discrete-Frequency S-parameters and Continuous-Frequency Responses
Peter J. Pupalaikis, LeCroy Corporation
