Congratulations to the 2010 DesignCon Paper Award winners in recognition for outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation at DesignCon 2010.

Chip-Level Design

Andres Takach, Chief Scientist, Design Creation and Synthesis, Mentor Graphics
Creating C++ IP for High Performance Hardware Implementations of FFTs

Luke Teyssier, Senior Staff Engineer, Differential Power Analysis, Cryptography Research
Strong Encryption and Correct Design Are Not Enough: Protecting Your Secure System from Side Channel Attacks

Board and System Design

Al Horn, Associate Research Fellow, Rogers Corporation
John W. Reynolds, Rogers Corporation
Patricia A. LaFrance, Rogers Corporation
James C. Rautio, Sonnet Software
Effect of Conductor Profile on the Insertion Loss, Phase Constant, and Dispersion in Thin High Frequency Transmission Lines

Kevin Hinckley, Signal Integrity Engineer, Sun Microsystems
Douglas Winterberg, Signal Integrity Engineer, Sun Microsystems
Mike Ballou, RF and Microwave Applications Engineer, Agilent Technologies
Gustavo Blando, Principal Engineer, Sun Microsystems
Jason Miller, Senior Staff Engineer, Sun Microsystems
Roger Dame, Member of Technical Staff, Sun Microsystems
Gregory Truhlar, Signal Integrity Engineer, Sun Microsystems
Alexander Nosovitski, Signal Integrity Engineer, Sun Microsystems
Shelley Begley, Application Development Engineer, Agilent Technologies
Istvan Novak, Distinguished Engineer, Sun Microsystems
Introduction and Comparison of an Alternate Methodology for Measuring Loss Tangent of PCB Laminates

Interconnect Design

Eric Bogatin, President, Bogatin Enterprises
Don DeGroot, President, CCN-i
Colin Warwick, Sr. Product Marketing, Agilent
Sanjeev Gupta, Agilent
Frequency Dependent Material Properties: So What?

Jason Miller, Senior Staff Engineer, Sun Microsystems
Gustavo Blando, Principal Engineer, Sun Microsystems
Istvan Novak, Distinguished Engineer, Sun Microsystems
Additional Trace Losses due to Glass-Weave Periodic Loading

High-Speed Design and Test Category

Ransom Stephens, Applied Electrodynamics Physicist, Ransom's Notes
John Calvin, Principal Engineer, Tektronix Instruments
A New Method for Receiver Tolerance Testing Using Crest Factor Emulation

Istvan Novak, Distinguished Engineer, Signal and Power Integrity, SPARC Volume Servers, Sun Microsystems
Yasuhiro Mori, Senior Product Manager, Agilent Technologies
Michael Resso, Signal Integrity Specialist, Agilent Technologies
Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range

Power and RF Design Category

Shishuang Sun, Member of Technical Staff Engineer, Altera Corporation
Larry D. Smith, Signal and Power Integrity Architect, Altera Corporation
Peter Boyle, Product Engineering Manager, Altera Corporation
On-Chip PDN Noise Characterization and Modeling

Xiaoxiong (Kevin) Gu, Research Staff Member, IBM T. J. Watson Research Center
Renato Rimolo-Donadio, Ph.D. Student, Technische UniversitŠt Hamburg-Harburg
Zhenwei Yu, Ph.D Student, Missouri University of Science and Technology
Francesco de Paulis, Ph.D Student, University of L'Aquila
Young H. Kwark, IBM
Matteo Cocchini, IBM
Mark B. Ritter, IBM
Albert Ruehli, IBM
Bruce Archambeault, IBM
Jun Fan, MST
Christian Schuster, TUHH
Fast Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis