IP and SoC designers make daily use of EDA flows that are sophisticated, heterogeneous and expensive. Too often, even these extensive tools are not enough to deliver high quality/ low risk implementation within very tight schedules in the face of increased design size and complexity. Panelists will use real-world examples to discuss: design quality issues arising from the increase in worldwide design teams; how to balance the costs of addressing quality design and IP up front vs. after tape-out; whether it's possible for management and design engineers to check quality continuously without adding to the design schedules and costs; the challenges of implementing fact-based design quality closure; how to measure quality improvements; how to decide which quality issues to address; and how helpful emerging quality standards are to address key issues.

Mr. Wilson has over 20 years of experience editing & reporting on the engineering & engineering management & 10 years experience in high-tech engineering & marketing. He has been Executive Editor of EDN since January 2006.

Camille recently managed physical design, methodology and San Jose-based CAD support teams for custom and RTL flows at IDT including IP/tools. He has held management and engineering positions at Mos Tek, VLSI and Philips Semiconductors. Camille holds an MSEE from the University of Illinois and an MBA from Florida Atlantic University.

Piyush is responsible for Atrenta's strategic alliances with key members of the semiconductor supply chain. He has over 15 years of experience in various marketing and product management roles at Sequence Design, Senté, and Cadence Design Systems. Piyush holds a Masters in Computer Engineering from Iowa State University.

Before founding Satin IP, Michel was a director at Synopsys and founder and General Manager at Arcad SA until acquisition by Synopsys in 1994. Michel has a degree in Engineering and a PhD in Microelectronic Design from the Laboratory of Automatics and Microelectronics in Montpellier, France.

Mr. Eversmann is director, Professional Services and Product Marketing at Numetrics Management Systems. He is a senior member of the IEEE, and past member of Program Management Institute (PMI) and Product Development and Management Association (PDMA).

Mr. Eversmann was previously Director of Silicon Engineering at ZiLOG, Inc. and site manager for ZiLOG's Seattle Design Center. He has extensive design experience in ASICs, microprocessors, and microcontrollers and has published conference papers in the areas of ASIC design flows, intellectual property, and design reuse.