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VERSION:2.0
METHOD:PUBLISH
BEGIN:VEVENT
CLASS:PUBLIC
PRIORITY:3
SEQUENCE:0
UID:101201089
SUMMARY:DesignCon 2010 - TP-W1 | Getting to Design Quality Closure Without Compromising Productivity 
LOCATION:Santa Clara Convention Center, Santa Clara, California 
DTSTART:20100203T214500Z
DTEND:20100203T230000Z
DTSTAMP:20100203T190034Z
DESCRIPTION:IP and SoC designers make daily use of EDA flows that are sophisticated, heterogeneous and expensive. Too often, even these extensive tools are not enough to deliver high quality/ low risk implementation within very tight schedules in the face of increased design size and complexity. Panelists will use real-world examples to discuss: design quality issues arising from the increase in worldwide design teams; how to balance the costs of addressing quality design and IP up front vs. after tape-out; whether it's possible for management and design engineers to check quality continuously without adding to the design schedules and costs; the challenges of implementing fact-based design quality closure; how to measure quality improvements; how to decide which quality issues to address; and how helpful emerging quality standards are to address key issues.
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