Chairperson:

Per Viklund
Director SiP and Advanced Packaging
Mentor Graphics Corporation

Per Viklund is a long time IEEE & IMAPS member with more than 25 years experience in electronic design automation (EDA) with 20+ years with design of advanced EDA tools. He is a recognized industry expert in advanced packaging and RF design and has published and presented numerous papers on IC packaging, embedded passives, RF and high speed design. Prior to joining Mentor, Viklund was chief technical manager of DDE-EDA for 10+ years.

A member of IEEE & IMAPS member with more than 25 years experience in EDA, and 20+ years experience in design of advanced EDA tools. A recognized industry expert in advanced packaging and RF design and and published author of papers on IC packaging, embedded passives, RF and high speed design.

Speakers:

John Park
Business Development Manager
Mentor Graphics

John Park brings over 25 years of EDA design tool experience to his role as Business Development Manager for the System Design Division at Mentor Graphics.

His hands-on design experience in IC place & route, IC Package design & modeling and PCB layout has allowed him to develop detailed cross-platform solutions that have helped define and drive the co-design market. In his current role at Mentor, he is focused on IO planning and advanced IC packaging technologies.

Robert Patti
Chief Technology Officer
Tezzaron Semiconductor Corp.

Bob Patti attended Rose-Hulman Institute of Technology, earning bachelor of Science degrees in both physics and electrical engineering. He founded an R&D company specializing in high-performance systems and ASICs and participated in the design of over 100 chips in the course of 12 years. Tezzaron Semiconductor grew from that company to become a leading force in 3D-IC technology. Today Bob serves as CTO of Tezzaron, using wafer-level stacking processes to create ultra high-density 3D memory products and other semiconductor sub-components. He is Vice-Chairman of JEDEC's DDRIII / Future Memories Task Group and holds 14 US patents, numerous foreign patents, and many more pending patent applications in deep sub-micron semiconductor chip technologies.

Riko Radojcic
Director of Through Silicon Stacking Initiatives
Qualcomm

Riko Radojcic is a leader of various Design-for-Technology initiatives at Qualcomm CDMA Technologies, addressing design for 3D integration, manufacturability, and variability methodologies at polygon, circuit, logic, and system design levels.

Radojcic has more than twenty-five year's experience in the semiconductor industry, specializing in the integration of process, design and EDA considerations, and design-for-Si solutions. Before joining Qualcomm, he was a consultant to semiconductor and EDA companies providing engineering and business development services focused on process-design integration. He was a director of business development and marketing for DFM solutions at PDF Solutions and was a business manager and an architect with Tality and Cadence, specializing in design technology integration and process characterization and modeling.

Radojcic has held a series of managerial and engineering positions with Unisys and Burroughs, in device engineering, failure analyses and reliability engineering areas. He began his career as a process engineer with Ferranti Electronics, UK.

Radojcic received his BSc and PhD degrees from University of Salford, UK.

E. Jan Vardaman
President and Founder
TechSearch International, Inc.

E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, MEPTEC, and SEMI. She received the "Die Products Industry Achievement Award," at the 14th Annual International KGD Packaging and Test Workshop in September 2007. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry's first pre-competitive research consortium.

Vern Wnek
C.I.D Manager, PCB Layout, ENG BU / Central Library
Manager Board and Package Design
Broadcom

Vern Wnek, CID, is a PCB Manager and the Central Library Manager for Broadcom Corporation in Irvine, CA. He has 30 years experience in the industry with PCB Layout Designs and EDA tools for DFM, DFA, and DFT requirements and is a multiple Co-Patent holder for Routing Optimization for Ball Grid Array Packaging for PCB Design.