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TP-M1 | Technical Panel
The Case of the Shrinking Eye: How Do We Keep Our Shrinking Eyes Open in the Face of Rising Signal Complexity?
Monday, February 1 | 4:45 pm - 6:00 pm

With serial data signaling approaching 8 GB/sec and causing serious signal integrity issues, characterization tools supporting equalization and fixture de-embedding are now required in order to observe the impacts of these signal integrity issues on your total system performance. Learn how today's leading designers are attacking this problem and what the T&M leaders have to say about testing solutions.

Chairperson:

Loberg Christoph Chris Loberg
Senior Manager, Business Instruments
Tektronix

Mr. Loberg is the Worldwide Senior Manager of Marketing for Performance Instruments at Tektronix. He holds an MBA in Marketing from San Jose State University and resides with his family in Beaverton, Oregon.

Speakers:

Eric Kvamme Eric Kvamme
Principal Engineer, SerDes Design
LSI Corp.

Mr. Kvamme has more than 19 years experience in the mass storage industry and with physical interfaces. His focus has been on interface signal integrity, characterization, and industry standards definition. He authored the ATA/66, 100, and 133 extensions to the ATA/ATAPI specification and was a leading participant in the SATA Electrical, Jitter, and Measurement subcommittees during the development of SATA. His current work involves developing and automating specification compliance and characterization test methods for bench testing high speed serial interface hardware. He holds B.S. and M.S. Engineering degrees from Harvey Mudd College (1989/1990).

Brian Fetz Brian Fetz
Serial Applications Product Manager, High Performance Oscilloscopes
Agilent Technologies

Mr. Fetz graduated from California Polytechnic State University at San Luis Obispo in 1983 and completed a Masters in Electrical Engineering from the University of Idaho in 1991. Before his current position, he worked on Agilent's Bluetooth and Signal Integrity solutions and prior to that his focus was in manufacturing where he has worked as a production engineer and test engineer for Base Station and Mobile testing products.

Mike Peng Li Mike Peng Li
Principal Architect
Altera

Dr. Mike Peng Li is a corporate expert and adviser on jitter, noise and high-speed link, and SERDES architecture. He is co-chairman for PCI Express jitter standard committee. In 2007, Dr. Li was chief technology officer at Wavecrest Corporation.

Mark Marlett Mark Marlett
Senior Principal Engineer
Xilinx

Mark is a SERDES Architect at Xilinx with 20 years of SERDES design experience. His primary focus on circuit topology, standards and manufacturability of SERDES. Mark has contributed to PCIE gen 1.1 and gen2. Fibre Channel, SAS, SATA in the areas of jitter decomposition and measurement.

Martin Miller Martin Miller
Chief Scientist
LeCroy

Dr. Miller has been a hands-on engineer and designer at LeCroy for 29 years. He has contributed analog, digital, and software designs, and during the last 16 years, he has focused on measurement-and-display software capabilities for LeCroy scopes.

Ransom Stephens Ransom Stephens
Applied Electrodynamics Scientist
Ransom's Notes

Dr. Stephens' company, Ransom's Notes, produces and presents content at every level of technical sophistication to help engineers advance to technology's cutting edge. He is the author of more than 200 articles in the electronics industry, science journals, and magazines.

Tom Waschura Tom Waschura
CTO
SyntheSys Research

With over 25 years experience in BER measurements and 12 patents, Tom and his team create measurement methods for testing serial streams with emphasis on high-fidelity bit decision. Author of many articles, webcasts and app. notes, Tom holds CS and EE degrees from Hiram College, M.I.T. and Stanford.

Pavel Zivny Pavel Zivny
Senior Product Engineer
Tektronix

Mr. Zivny works with the sampling oscilloscopes group of Tektronix. Over the years he has been involved in test, design, and marketing of both real-time and sampling oscilloscopes, and has several oscilloscope-related patents awarded and pending.

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