TF-TH1

Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs

Thursday, February 4, | 9:00 am – 12:00 pm

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Larry Smith, Signal and Power Integrity Architect, Altera Corporation
Jim Antonelis, Principal Engineer, Broadcom Corporation
Rick Brooks, Manager of Hardware Engineering, Cisco Systems
Souvik Mukherjee, CAD/Methodology Engineer, WTBU, Texas Instruments
Ji Zheng, Director of Chip-Package-System, Apache Design Solutions

Chip, package and board designs cannot happen in isolation given performance and cost considerations. An analysis and verification methodology that targets power delivery and signal integrity in a co-design framework is required to ensure that the system performance specifications are met at the lowest design and material costs. For example, for power delivery network design, an analysis environment that accurately models the chip, package and board and allows for multiple analyses (DC, AC and transient) concurrently is required. Similarly, for signal integrity especially for high speed IO interfaces, the simultaneous consideration of the IO ring design, IO and decoupling capacitor cell placement, input switching pattern, and package/board power and signal layouts is necessary.

In this workshop, chip-package-board analysis methods for both power and signal integrity will be discussed in terms of modeling, extraction and simulation technologies. Representatives from key semiconductor and system design companies will participate to share their insights into these techniques. Below are brief description of the industry representative's viewpoints that will be shared during the workshop.

Larry Smith, Altera Corporation

There are two major frequency bands of interest for the PDN: first dip and die/package resonance. The first dip is associated with a clock edge and occurs because a certain amount of charge is drawn by the load with a rise time on the order of 100pSec. All the charge consumed in this time period must already be in capacitance on the die because the package is too slow to respond. At a much lower frequency, the on-die capacitance resonates with the package inductance, typically around the 30 MHz band. The PDN resonant system involves the die, package and board. It is not possible to analyze the die/package/board resonance problem without viewing the PDN as a system. Tools to analyze the 30 MHz band problem may be related to but are different from the tools required for the GHz problem.

Jim Antonelis, Broadcom Corporation

Broadcom Enterprise Networking Switch Group is committed to enhancing the customers ability to perform System Level Power Integrity (PI). Towards that goal, system level PI analyses are performed using package, board and die models. In this presentation Broadcom will illustrate a 3-facet, System Level, Power Integrity Analysis composed of DC, AC and Transient analyses targeting specific goals. A methodology for these simulations will be shown along with system level analysis results.

Souvik Mukherjee, Texas Instruments

The design of IC, package, and PCB for wireless applications is aggressively driven by cost in addition to performance due to competitive market forces and the consumer business model. In such a case, it is imperative to perform accurate 3D modeling of the electromagnetic environment of the PCB and package, accurate and distributed extraction of the IC power-grid and efficient simulation strategies with the models to evaluate system performance. To that end, the presentation focuses on some of the key challenges around system-level modeling, extraction and simulation and time-domain vs frequency-domain characterization. Additionally, the presentation focuses on design abstraction needs at pre-layout vs post-layout phase and the need for accurate measurement-based benchmarking.