Mike Li, Principle Architect/Distinguished Engineer, Altera

This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and deep submicron process technology advancements for high-speed links, with an emphasis on jitter and signal integrity for ~10-Gbps high-speed I/Os (e.g., GBE (10G, 40G/100G), CEI/OIF (11+G), Fibre Channel (8.5G), and PCI (8G)). Example studies on design and validation methods will be presented, as well as the practical issues of design tradeoff, multiple I/O standards support, jitter reduction, signal integrity mitigation, and advanced verification methodologies. Finally, a forward-looking overview for the next-generation high-speed I/O standards (e.g., CEI/OIF 25-28G, Fibre Channel 14G) and associated jitter and signal integrity challenges will be presented.