Bhanu Kapoor, Consultant/Owner, Mimasic
Dr. Shireesh Verma, Verification Manager, Conexant
Prapanna Tiwari, Staff CAE, Synopsys Inc.
Dr. Kaushik Roy, Professor, Purdue University
Amit Kumar, Senior Program Manager, SiRF Technologies

Power consumption has become one of the most important differentiating factors for semiconductor products. Voltage is the strongest handle for managing chip power consumption. We look in detail at some of key power management techniques such as Power Gating, Adaptive Voltage Scaling and Active Body-Bias that leverage voltage as a handle.

We discuss the implications of power management architecture design, partitioning and new challenges in functional validation. We look at top power management verification issues such as reset out of wake-up, power connectivity, always-on buffers, switching management, state retention and sequencing protocol, and decap placement issues in detail.