DesignCon 2010 - Attendees

Program Schedule

View options:		All		Monday		Tuesday		Wednesday		Thursday

Monday, February 1

9:00 am – 12:00 pm		TF-MA1 \| Tutorial Clock Concurrent Optimization Rethinking Timing Optimization to Target Clocks and Logic at the Same Time

		TF-MA2 \| Tutorial Navigating Electromagnetic Field Solvers: Designer and EDA Perspectives

		TF-MA3 \| Tutorial USB 3.0 Verification and Test Challenges

		TF-MA4 \| Tutorial Top System-On-a-Chip Power Management Verification Issues and Their Solutions

		TF-MA5 \| Tutorial Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm

		TF-MA6 \| Tutorial Best Practices for IP Re–Use

12:00 pm – 1:00 pm		Monday Keynote Luncheon Speaker: Jure Sola, Chairman and Chief Executive Officer, Sanmina-SCI

1:30 pm – 4:30 pm		TF-MP1 \| Tutorial Functional Verification Planning and Management For Designers: Navigating From Specification to Functional Closure

		TF-MP2 \| Tutorial Designing PCB Stackups to Balance Signal Integrity Against Manufacturability

		TF-MP3 \| Tutorial Active Cable Interconnects for High-Speed Serial Communications

		TF-MP4 \| Tutorial Design and Verification for High-Speed I/Os at Multiple to >10 Gbps with Jitter and Signal Integrity Optimization

		TF-MP5 \| Tutorial New Solutions Technologies for EM Simulation: What the SI Engineer Needs to Know... But Was Afraid to Ask

		TF-MP6 \| Special Session Comparison of Rapid Solution Techniques for Power Integrity Organizer: Bruce Archambeault, Distinguished Engineer, IBM

		Agilent Educational Forum Practical Magic: Signal Integrity Problems Disappear Using the Right Tools Presenter: Eric Bogatin, President, Bogatin Enterprises

4:45 pm – 6:00 pm		TP-M1 \| Technical Panel The Case of the Shrinking Eye: How do we keep our shrinking eyes open in the face of rising signal complexity? Chairperson: Chris Loberg, Senior Manager, Business Instruments, Tektronix

		TP-M2 \| Technical Panel Making Sense out of Dielectric Loss Numbers, Specifications and Test Methods Chairperson: Istvan Novak, Distinguished Engineer, SPARC Volume Servers, Sun Microsystems

Tuesday, February 2

8:30 am – 9:10 am		1-TA1 Accurately Timing Analyzing Memory Interfaces in the Presence of Calibrated Paths

		2-TA1 VIA-Configurable Analog ASICs: Technology and Applications

		5-TA1 Effect of conductor profile on the insertion loss, phase constant, and dispersion in thin high frequency transmission lines

		7-TA1 Frequency Dependent Material Properties, So What?

		10-TA1 Estimation of Simultaneous Switching Noise from the Power Distribution Network Impedance in LPDDR2 Systems

		12-TA1 Evaluation of Relative Humidity and Temperature Effects of Scattering Parameters on Transmission Systems (0-26 GHz)

9:00 am – 10:00 am		BF-T1 \| Business Forum Outsourcing the Electronics Design Chain for Efficiency & Profitability

9:20 am – 10:00 am		1-TA2 Functional Verification of Highly Parameterizable IP and System-level Design-Assembly Tools for FPGAs

		2-TA2 A 10GHz Multi-Rate Low-Jitter PLL in 40nm CMOS Technology for PCIe Gen1/2/3 and 10Gbps SerDes

		5-TA2 Impact of Copper Surface Texture on Loss: A Model that Works

		7-TA2 Optoelectronic Hybrid Backplane Platform Technology for 100G Ethernet Switch/Router

		10-TA2 Simulation and measurement of an on-die power gated power delivery system

		12-TA2 PWB Manufacturing Variability Effects on High Speed SerDes Links: Statistical Insights from Thousand

10:10 am – 10:50 am		2-TA3 Phase-Noise Characterization for RF Oscillators with Bandgap Reference and Isolation Buffer

		5-TA3 Matched Terminated Stub VIA Technology for Higher Bandwidth Transmission in Line Cards and Backplanes

		7-TA3 When Shorter isn't Better

		8-TA3 Power Integrity and Noise Coupling Effects on Signal Integrity - Methodology for Identifying the Deterministic Jitter Components and their Generating Sources in Data Communication Systems

		10-TA3 On-chip PDN Noise Characterization and Modeling

		11-TA3 EMC and SI issues and their resolution in Multi-Gbps Telecommunications Blade System

10:10 am – 11:40 am		BF-T2 \| Business Forum Exploring the Business Aspects for 3-D Device Success

11:00 am – 11:40 am		1-TA4 Leveraging Simulation Tools in FPGA Lab Debug

		2-TA4 Analog Mixed Signal Full-link Analysis of Quick Path Interconnect

		5-TA4 Cost Effective Crosstalk Management & Decision Making

		7-TA4 Simulation Techniques for 6+ Gbps Serial Links

		8-TA4 A New Crosstalk Jitter Separation Method

		10-TA4 Statistical Simulation of Simultaneous Switching Output Noise

		11-TA4 Building IC-Package-PCB System EMI/EMC Verification and Early Design Flows: Challenges and Methods

12:00 pm - 12:30 pm		Tuesday Keynote Address Speaker: Vince Hu, Vice President, Product and Corporate Marketing, Altera Corporation

12:30 pm - 6:30 pm		Technology Exhibition (Lunch served on the exhibit floor from 12:30 pm – 2:00 pm)

1:30 pm – 1:50 pm		TecPreview Dealing with Noise and Signal Loss

2:00 pm – 2:20 pm		TecPreview Easy S-Parameter Measurement for Signal Integrity Engineers Speaker: Michael Schnecker , Business Development Manager, LeCroy Corporation Michael Schnecker is a Business Development Manager at LeCroy Corporation. Mr. Schnecker specializes in signal integrity measurements including jitter and has been instrumental in specifying and deploying the LeCroy SDA series instruments. He holds a BS degree from Lehigh University and MS degree from the Georgia Institute of Technology both in electrical engineering and has 18 years of experience in the test and measurement industry.

2:00 pm - 2:40 pm		1-TP1 Designing Scalable Wireless Application-Specific Accelerators Using PICO High Level Synthesis

		2-TP1 An Optimizer-Assisted Design Methodology For A Two Stage Wideband Feedback Amplifier

		4-TP1 Electrical Evaluation of Power-Grid Configurations

		5-TP1 A Systematic Approach to PCB Material Characterization Using Time Domain TRL Calibration

		13-TP1 Higher Speed Ethernet - 40 Gb/s and 100 Gb/s copper cable assembly specifications

2:00 pm – 3:30 pm		BF-T3 \| Business Forum Panel The Last Mile: Outsourcing Production

2:30 pm – 2:50 pm		TecPreview Ticona Engineering Polymers TecPreview Presentation: Engineering Polymer Solutions for Lead-free Solderable Components

2:50 pm – 3:30 pm		1-TP2 Offset Cancellation in Receiver Path in 45-nm 6.5-Gbps Transceiver FPGAs

		4-TP2 Design and Characterization of a 12.8GB/s Low Power Differential Memory System for Mobile Applications

		5-TP2 Introduction and Comparison of an Alternate Methodology for Measuring Loss Tangent of PCB Laminates

		8-TP2 Rigorous Modeling of Transmit Jitter for Accurate and Efficient Statistical Eye Simulation

		13-TP2 Chip-to-Chip Communication Beyond 25 Gbps - Modeling and Realization

3:00 pm – 3:20 pm		Vitesse Semiconductor TecPreview Presentation Measurement Resolution and Accuracy for Vscope^TM Embedded Waveform Viewing Technology

3:45 pm – 5:00 pm		Business Forum Panel Science Fiction... Is it Really Fiction? Chairperson: Gabe Moretti, Owner, GabeOnEDA

3:45 pm – 5:00 pm		TP-T2 \| Technical Panel SiP and Advanced Packaging - A Growing Market Segment in an Economic Downturn - Turning to 3D Packaging Chairperson: Per Viklund, Director, SiP and Advanced Packaging, Systems Design Division, Mentor Graphics Corporation

3:45 pm – 5:00 pm		TF-T3 \| Technical Panel Extent of Dynamic Validation in Power Managed Designs Chairperson: Bhanu Kapoor, President and Founder, Mimasic

5:00 pm – 6:30 pm		Networking Reception

Wednesday, February 3

8:30 am – 9:10 am		1-WA1 Evolving throughput Driven Architecture for Error Correction in NAND Memory

		4-WA1 Multi-GHz On-Chip Power Grid Modeling Method

		6-WA1 Crosstalk Decomposition and the Triangle Inequality Property of Peak Distortion Analysis

		7-WA1 Additional Trace Losses due to Glass-Weave Periodic Loading

		9-WA1 Hybrid Statistical and Time-domain Simulation Methodology for High-speed Links

		13-WA1 Fast Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis

8:30 am – 11:30 am		Agilent Educational Forum Practical Magic: Signal Integrity Problems Disappear Using the Right Tools Presenter: Eric Bogatin, President, Bogatin Enterprises

9:20 am – 10:00 am		3-WA2 A Spreadsheet-Based Executable Specification For Scalable Multi-Million Gate SOC Design

		4-WA2 An Accurate Methodology for Model-to-hardware Calibration and Correlation with PCB-package Mimulation Using Electromagnetic Solvers

		6-WA2 Timing Measurement Problems and Solutions in Source Terminated Memory Systems with Inaccessible Probing Points

		7-WA2 Skew Impact Estimation on High Speed Serial Channels Using Mathematical Analysis and Accurate Lab Measurements

		9-WA2 Cu Cable Study at 10GbE Data Rate Utilizing the Latest Technologies for Advanced Equilizers and Passive Cu Cable Assemblies to close on a 20m Link

		12-WA2 Practical Identification of Dispersive Dielectric Models with Generalized Modal S-parameters for Analysis of Interconnects in 6-100 Gb/s Applications

10:10 am 11:40 am		BF-W2 Total IP Solutions Required to Ease SoC Integration

10:10 am - 10:50 am		4-WA3 Analysis of FPGA PDN Noise Propagation by die/package 3D Modeling

		6-WA3 Budgeting and Measuring a High Speed Graphics Memory Interface

		7-WA3 Practical Limitations of Backplane Architectures for 20 Gbps and Above

		9-WA3 A Tale of Long Tails

		10-WA3 Reducing Hotspots in Backplane Power Distribution

		12-WA3 Compliance Testing of Passive Interconnects

11:05 am – 11:45 am		Achieving Interoperability of the VIP Across the Big 3 Simulators

11:00 am – 11:40 am		4-WA4 A Case Study of Multi-Chip Package Signal and Power Integrity Optimization and Tradeoff

		6-WA4 Interconnect Considerations for DDR Timing Closure beyond 1600Mbps

		7-WA4 Required Technologies for Transmission of 4 x 25 Gb/s Over a Copper Backplane

		9-WA4 Is Hybrid Combination of Viterbi Detector and Decision Feedback Equalizer feasible in Electrical SerDes?

		11-WA4 Shielded Flex Circuitry, What Drives Performance?

		12-WA4 Practical Study of Appropriate Measurement Bandwidth and Noise, along with its Impact on Oscilloscope based Time and Frequency Measurements

12:00 pm – 12:30 pm		Wednesday Keynote Address Speaker: Alex Shubat , President and Chief Executive Officer, Virage Logic

12:30 pm – 6:30 pm		Technology Exhibition (Lunch served on the exhibit floor from 12:30 pm – 2:00 pm)

2:00 pm – 2:20 pm		TecPreview Mentor Graphics TecPreview Presentation: What engineers need to know about SERDES, SPICE, and IBIS–AMI

2:00 pm – 2:40 pm		1-WP1 Creating C++ IP for High Performance Hardware Implementations of FFTs

		4-WP1 Efficient Modeling and Simulation for Package-PCB Co-Design and Co-Optimization

		6-WP1 Required Technologies for Transmission of 4 x 25 Gb/s Over Copper Cable

		7-WP1 Technical Considerations in System Integration of EDC IC's in 8G Fibre Channel Applications

		8-WP1 A New Method for Receiver Tolerance Testing Using Crest Factor Emulation

		12-WP1 SET2DIL: Method to Derive Differential Insertion Loss from Single-Ended TDR/TDT Measurements

		13-WP1 An Effective Methodology to Improve Impedance Transparency for AC-Coupling Capacitors in 10 Gbps SerDes Channel

2:00 pm – 3:30 pm		BF-W3 \| Business Forum Panel Next Wave: SoC Architecture, Standards and Tools Speed Application-driven Ecosystem Solution Development

2:50 pm – 3:30 pm		1-WP2 Transaction-Level Modeling of DRAM-Subsystems for Performance-Analysis

		5-WP2 Electrical Characterization of Flexible Circuit Materials at High Frequency

		4-WP2 Block Level Analysis of Chip and System Level Resonances

		6-WP2 Study of a Dynamic Point to Point Technology Using Flex Interconnect for Computer Main Memory Applications Supporting Data Rates of up to 16 Gbps

		11-WP2 Application of Full-wave 3D Field Solvers to Predict EMI Behavior in SFP Cages

3:45 pm – 5:00 pm		Technical Panel Getting to Design Quality Closure without Compromising Productivity Chairperson: Ron Wilson, Executive Editor, EDN Worldwide

		Technical Panel Meeting Chip to Chip I/O Demands of 100G & Beyond Line Cards Chairperson: Jag Bolaria, Senior Analyst, The Linley Group

		Technical Panel Challenges of Applying Statistical Analysis Techniques in High Speed Serial Channel Design Chairperson: Dan Oh, Senior Principal Engineer, Rambus

		Business Forum Panel Social Media—Do We Really Have to Do It? Chairperson: Dean Solov, Senior Public Relations Manager, Corporate Communications, Cadence Design Systems

5:00 pm – 6:30 pm		Exhibits and Reception

Thursday, February 4

9:00 am – 9:40 am

1-TH1

How to Tune Your SoC to Avoid Traffic Congestion

7-TH1

Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement

10-TH1

Power Delivery Network Optimization for Laptop and Desktop Computer Platforms

9:00 am – 12:00 pm

TF-TH1

Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs

Listen here for podcast preview

9:50 am – 10:30 am

1-TH2

Automatic Quantitative Analysis of Simulations of TLM 2.0 Loosely Timed Models

7-TH2

Full-wave Time Domain Modeling of Interconnects

10-TH2

nm-Systems' Jitter Resonance Induced by PDN Noise of toggling on-die Logic

10:40 am – 11:20 am

1-TH3

Strong Encryption and Correct Design is not Enough: Protecting Your Secure System From Side Channel Attacks

7-TH3

Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels

10-TH3

On-Chip Power Supply Noise and Reliability Analysis for Multi-Gigabit I/O Interfaces

12-TH3

Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range

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View the Exhibitor Product Guide

FEATURED EVENTS

OFFICIAL HOST SPONSOR

IP SUMMIT SPONSOR

CORPORATE PARTNER

DIAMOND SPONSORS

GOLD SPONSORS

SILVER SPONSORS

CORPORATE REGISTRATION SPONSORS

9:00 am – 12:00 pm		TF-MA1 \| Tutorial Clock Concurrent Optimization Rethinking Timing Optimization to Target Clocks and Logic at the Same Time

		TF-MA2 \| Tutorial Navigating Electromagnetic Field Solvers: Designer and EDA Perspectives

		TF-MA3 \| Tutorial USB 3.0 Verification and Test Challenges

		TF-MA4 \| Tutorial Top System-On-a-Chip Power Management Verification Issues and Their Solutions

		TF-MA5 \| Tutorial Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm

		TF-MA6 \| Tutorial Best Practices for IP Re–Use

12:00 pm – 1:00 pm		Monday Keynote Luncheon Speaker: Jure Sola, Chairman and Chief Executive Officer, Sanmina-SCI

1:30 pm – 4:30 pm		TF-MP1 \| Tutorial Functional Verification Planning and Management For Designers: Navigating From Specification to Functional Closure

		TF-MP2 \| Tutorial Designing PCB Stackups to Balance Signal Integrity Against Manufacturability

		TF-MP3 \| Tutorial Active Cable Interconnects for High-Speed Serial Communications

		TF-MP4 \| Tutorial Design and Verification for High-Speed I/Os at Multiple to >10 Gbps with Jitter and Signal Integrity Optimization

		TF-MP5 \| Tutorial New Solutions Technologies for EM Simulation: What the SI Engineer Needs to Know... But Was Afraid to Ask

		TF-MP6 \| Special Session Comparison of Rapid Solution Techniques for Power Integrity Organizer: Bruce Archambeault, Distinguished Engineer, IBM

		Agilent Educational Forum Practical Magic: Signal Integrity Problems Disappear Using the Right Tools Presenter: Eric Bogatin, President, Bogatin Enterprises

4:45 pm – 6:00 pm		TP-M1 \| Technical Panel The Case of the Shrinking Eye: How do we keep our shrinking eyes open in the face of rising signal complexity? Chairperson: Chris Loberg, Senior Manager, Business Instruments, Tektronix

		TP-M2 \| Technical Panel Making Sense out of Dielectric Loss Numbers, Specifications and Test Methods Chairperson: Istvan Novak, Distinguished Engineer, SPARC Volume Servers, Sun Microsystems

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