Today's high speed digital design engineers are faced with ever increasing data rates that create a multitude of challenges: interconnects become microwave transmission lines, reflections wreak havoc on timing margins and jitter closes the eye diagram. In addition, higher data rates dictate that measurements and models must correlate with each other to ensure the digital system works at all. Where to begin? This educational forum will show a typical design flow and show how to solve the most common problems that arise. Experts will explain when to use which design tool and how to use it. De-embedding is one of the most misused and misunderstood tools inside the signal integrity lab today, so we will show real world examples of how various types of de-embedding can increase measurement accuracy, shorten the design cycle and maximize efficiency. This forum will also present examples of pre-layout methods, post-layout board simulation, S-parameter data mining and show how to optimize vias, connectors and PCB traces.