Brian Kirk, Signal Integrity Engineer, Amphenol TCS
Jose Paniagua, Signal Integrity Engineer, Amphenol TCS
Vijay Kasturi, Signal Integrity Engineer, Amphenol TCS
Meilin Wu, Signal Integrity Engineer, Amphenol TCS

With multiple different protocols at or above 10 Gbps already deployed on copper backplanes, systems are now being designed to support 20 Gbps and above. Copper backplane links are typically designed to support multiple generations of successive increases in bandwidth. Consequently, this leads to the inevitable question of how to increase the backplane architecture beyond 20 Gbps. This paper investigates all passive components of the high-speed serial backplane interconnect with particular emphasis on data rate versus density trade-offs. The practical constraints of current manufacturing processes, material limitations, and cost are all explored with respect to signal quality approaching 40 Gbps.