Donald Telian, SI Consultant, SIguys
Sergio Camerlo, Engineering Director, Ericsson
Brian Kirk, SI Engineer, Amphenol-TCS

This paper details a thorough process for serial link SI analysis in the 6+ Gbps range - from modeling to measurement. Proper modeling techniques for both the active (SerDes, AMI, transistor-level, etc) and passive (3D extraction, S-parameters, parasitics, etc) devices are described, along with solutions for making progress when desired models are not available. Sensitivity analysis reveals variables that limit system performance and guides design choices to optimize the link - adding as much as 50% more system margin. With variables and tolerances understood, thorough worst-case analysis is performed to quantify anticipated design margin which is later confirmed through measurement.