Michael White, Analog Engineer, Platform Validation Engineering, Intel
Richard Mellitz, Principle Engineer, Intel
Dennis Miller, Senior Signal Integrity Engineer, Intel
Virapandiane Ragavassamy, Analog Engineer, Intel
Ted Ballou, Signal Integrity Engineer, Intel
Michael Brownell, Senior Package & Interconnect Engineer, Intel

This paper guides the board designer in making effective decisions concerning crosstalk management. It describes important coupling mechanisms in board designs, means of predicting crosstalk, and methods for determining routing length/performance impacts. To bring greater clarity to a complicated problem, it introduces the practice of crosstalk management based on a notion of equivalent routing length. The board designer often has limited scope for assessing crosstalk risk; design decisions aimed at layer count reduction, part selection and increasing system density often exacerbate coupling effects. The paper provides several case studies of problematic crosstalk scenarios.