Dan Oh, Senior Engineering Manager, Rambus Inc.
Sam Chang, Signal Integrity Engineer, Rambus Inc.
Chris Madden, Senior Principal Engineer, Rambus Inc.
Joong-Ho Kim, Principal Engineer, Rambus Inc.
Ralf Schmitt, Senior Engineering Manager, Rambus Inc.
Ming Li, Prinicipal Engineer, Rambus Inc.
Chuck Yuan, Engineering Director, Rambus Inc.
Fred Ware, Techinical Director, Rambus Inc.
Brian Leibowitz, Principal Engineer, Rambus Inc.
Yohan Frans, Senior Principal Engineer, Rambus Inc.
Nhat Nguyen, Senior Engineering Manager, Rambus Inc.

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is described and its performance is analyzed. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.