Krishna Bharath, Packaging Engineer, Intel Corporation
Mahadevan Suryakumar, Engineering TD Manager, Intel Corporation
Ananda Sarangi, Analog Engineer, Intel Corporation

Scaling of transistor geometries has been the primary mechanism to support the exponential increase in microprocessor performance over generations. However, the metal interconnect and bump pitch have not scaled at the same rate, leading to challenges in power delivery. In this paper, conceptual designs have been explored to optimize the on-chip power-grid in conjunction with the package.