Yun Ji, Staff Signal Integrity Engineer, Intel Corporation
Das Ripan, Design Engineer, Intel
Yongping Fan, Design Engineer, Intel
Wei-hsing Huang, Signal Integrity Engineer, Intel
Chris Pan, Senior manager, Qualcomm

Intel's 6.4 GT/s Quick Path Interconnect(QPI) imposes new circuit/platform design and validation challenges due to its mixed signal design nature. The complexity of QPI analog and digital circuit design puts the full QPI link simulations well beyond the capability of traditional SPICE simulation engines and digital RTL validation flows. Analog Mixed Signal (AMS) analysis flow can significantly improve simulation efficiency and expose complex logic and electrical issues. This paper presents a bottom-up AMS simulation/validation methodology based on a schematic-driven approach, which improves simulation efficiency by 100 folds for functionality verification, and 10 folds for performance verification.