Chiang Pu, Technical Manager, TSMC
Pang-Cheng Hsu, Technical Manager, GUC
Chan-Hong Chern, Director, TSMC
Chih-Chang Lin
Joyce Huang
Ming-Chieh Huang

A multi-rate low jitter PLL intended for supporting PCIe gen1 to gen3 and 10Gbps SerDes applications is presented. The PLL design utilizes a single LC-tank VCO, with novel calibration circuits to automatically select VCO bands for various PCIE and high-speed SerdDes applications. Silicon measurement showing total jitter of 1.3ps(rms) is achieved. Total PLL power is 45mW @10GHz. Area is 0.36mmx0.36mm in TSMC 40nm technology. For circuit designs in advanced technologies (45nm and below), layout effect impacts become too significant to not being meticulously addressed. This paper also addresses layout effect impacts on designs.