Tina Tran, Senior Design Manager, Altera Corporation
Doris Chan, Design Engineer, Altera Corporation
Simar Maangat, Design Engineer, Altera Corporation
Toan Thanh, Member of Technical Staff, Altera Corporation
Sergey Shumarayev, Director of Engineering, Altera Corporation
Weichi Ding, Altera Corporation

As technology scales down from 90 nm to 40 nm, voltage offsets from the component mismatch caused by fabrication are getting worse. One metric of measuring the performance of the transceiver receiving path, affected heavily by this offset, is the minimum input voltage. With this voltage offset, input voltage must be raised to detect the data bit correctly. Furthermore, duty cycle distortion is introduced, which increases the bit error rate (BER) of the overall system. Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property (IP) core programmed in the programmable logic device.