Yang Sun, PhD student, ECE department, Rice University
Kiarash Amiri, PhD student, Rice University
Joseph R. Cavallaro, Professor, Rice University
Tai Ly, Senior Field Application Engineer, Synfora, Inc.

This paper presents a system level methodology of designing and exploring scalable and flexible wireless application-specific accelerators. Traditional hardware designs and implementations for wireless systems have a huge time gap between the development of algorithms for new wireless standards and their hardware implementation. Hardware designed using traditional HDL flows has such a long design time that by the end of the design cycle, the algorithms have already moved to the next wireless standard, out-dating the hardware design. The high level synthesis tools create application accelerators from high abstraction-level, un-timed C for complex processing hardware, which greatly reduce the design cycle while still maintaining area and power efficiency. This paper presents two complex wireless designs using program-in chip-out (PICO) high level synthesis methodology: 1) High performance multiple-input multiple-output (MIMO) detector design, and 2) High throughput low-density parity-check (LDPC) channel decoder design.