Torrey Lewis, Synopsys
Neil Songcuan, Product Marketing Manager, Synopsys

With increasing design complexity and limited simulation cycles, it becomes necessary to prototype designs. Lab debug tools have traditionally consisted of voltmeters, oscilloscopes and logic analyzers, rendering tools developed specifically for simulation (i.e. waveform viewer scripts, interface assertions, checkers and transaction monitors) unusable.

This paper documents how a new generation of FPGA debug tools leverage simulation tools in a complex FPGA design. Two categories of FPGA debug tools will be discussed. The first increases visibility into the design. The second replays transactions captured in the lab in the simulator, allowing for the use of a bus interface transaction monitor.