Jeffrey Fox, Principal Verification Architect, Altera Corporation
Kent Orthner, Manager, System Level Tools, Altera Corporation

Advances in verification technology for digital design, such as SystemVerilog Testbench and Assertions, combined with standardized class libraries and methodologies, such as VMM and OVM, have made it both practical and cost effective to obtain a high degree of confidence in the correctness of complex, highly configurable designs.

This paper describes how Altera is using advanced verification technology to create quantifiably correct, highly configurable and reusable IP as well as powerful, yet flexible, system-level design-assembly tools for field programmable logic devices.