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VERSION:2.0
METHOD:PUBLISH
BEGIN:VEVENT
CLASS:PUBLIC
PRIORITY:3
SEQUENCE:0
UID:101201017
SUMMARY:DesignCon 2010 - 1-TA2 | Functional Verification of Highly Parameterizable IP and System-level Design-Assembly Tools for FPGAs
LOCATION:Santa Clara Convention Center, Santa Clara, California 
DTSTART:20100202T152000Z
DTEND:20100202T160000Z
DTSTAMP:20100203T164634Z
DESCRIPTION:Advances in verification technology for digital design, such as SystemVerilog Testbench and Assertions, combined with standardized class libraries and methodologies, such as VMM and OVM, have made it both practical and cost effective to obtain a high degree of confidence in the correctness of complex, highly configurable designs.
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END:VCALENDAR